Contact Information
Avinash Karanth
Chair, Electrical Engineering and Computer Science
Joseph K. Jachinowski Professor in EECS
Associate Editor IEEE Transactions on Computers
School of Electrical Engineering and Computer Science Russ College of Engineering and Technology Ohio University 322D Stocker Center Athens, OH 45701
Office: STKR 322D
Tel: (740)-597-1481
Fax: (740)-593-0007
E-mail: karanth[at] ohio [dot] edu
Resume: CV
NEW: Postdoc position available, apply here

Biography
I received my PhD and MS from Electrical and Computer Engineering Department from The University of Arizona 
in August 2006 and May 2003 respectively. I completed my BE in Electronics and Communications in February 2000
from Manipal Institute of Technology, Mangalore University. I was a post-doctoral scholar at the High-Performance
Computing Architectures and Technologies (HPCAT) Laboratory at The University of Arizona from 2006 to 2007.
I was a consultant to Advanced Micro Devices (AMD) on Exascale and FastForward initiatives sponsored by
Department of Energy from 2013-2017.

Presently, I am the Chair of the School of Electrical Engineering and Computer Science as well as Joseph K. Jachinowski
Professor in the School of Electrical Engineering and Computer Science at Ohio University. I lead the Technologies
for Emerging Computer Architecture Laboratory (TEAL)
at Ohio University. I am Senior Member of the IEEE.

My research interests include computer architecture, optical interconnects, Network-on-Chips (NoCs) and emerging
technologies such as nanophotonics, 3D and wireless interconnects. I am the recipient of the
NSF CAREER Award
(2011), Presidential Research Scholar Award (2017),
Best Paper Award at the ICCD (2013) conference and my
papers have been nominated for Best Paper at IEEE Design and Test in Europe (DATE) in March 2019, IEEE

Symposium on Network-on-Chips (NoCs) in May 2010 and IEEE Asia & South Pacific Design Automation Conference
(ASP-DAC) in January 2009. My 2004 Hot Interconnects paper was selected as one of the Top Picks for IEEE MICRO
magazine in 2005.

I serve as an Associate Editor and Topical Editor for IEEE Transactions on Computers and I have been a co-Guest
Editor for IEEE Transactions on Emerging Topics for Computing ('15-'16) and Journal of Parallel and Distributed
(JPDC) ('10-'11). I am the Vice-Chair for Architecture area for IPDPS-2020 and I have been on the Program
Committee of HPCA'19, DAC ('18,'19,'20), NAS'17, NoCs ('16, '17, '18, '19), MPSoCs ('14, '15, '16, '17, '18, '19),
ACM Nanocom '16, Hot Interconnects ('10,'15,'16,'17), external Program Committee for MICRO'12 and HPCA'17.
Honors & Awards
Teaching - Fall 2021
Research Interests
Selected Recent Publications

Albiero: Energy-Efficient Acceleration of Convolutional Neural Networks via Silicon Photonics [ISCA'21]
Scaling Deep Learning Inference with Chiplet-based Architecture and Photonic Interconnects [DAC'21]
CSCNN: Algorithm-Hardware Co-Design for CNN Accelerators using Centrosymmetric Filters
[HPCA'21]
GCNAX: A Flexible Dataflow Accelerator for Graph Convolution Neural Network [HPCA'21]
PIXEL: Photonic Neural Network Accelerator [HPCA'20]
DoZZNoC: Reducing Static and Dynamic Energy in NoCs with Low-Latency Voltage Regulators using Machine Learning [IPDPS'20]
IntelliNoC: A Holistic Framework for Energy-Efficient and Reliable On-Chip Communication for Manycores [ISCA'19]
High-Performance, Energy-Efficient, and Fault-Tolerant Network-on-Chip Design using Reinforcement Learning [DATE'19, Nominated for Best Paper]

Last Updated Sept 1, 2021