JANUSZ A. STARZYK

VITA

 Friday March 12, 2010

 

ADDRESSES Electrical Engineering                            Home:

                                    Ohio University                         352 Carroll Rd.                                                                         

                                    Athens, OH 45701                     Athens, OH 45701

                                    (740)593-1580                           (740)593-7675

html: http://www.ent.ohiou.edu/~starzyk/             email: starzyk@bobcat.ent.ohiou.edu

 

EDUCATION

            M.Sc. in Applied Mathematics in Electrical  Engineering,

            Warsaw University of Technology, Warsaw, Poland, 1971.

Ph.D. in Electrical Engineering,

            Warsaw University of Technology, Warsaw, Poland, 1976.

Postdoctoral Fellow, Mc Master University, Hamilton, Canada, 1981-1982.

Habilitation in Electrical Engineering,

The Silesian University of Technology, Gliwice, Poland.

 

 

PROFESSIONAL EXPERIENCE

OHIO UNIVERSITY – School of Electrical Engineering and Computer Science

1983 – 1990:                 Associate Professor of Electrical Engineering.

1990- present:               Professor of Electrical Engineering and Computer Science.

 

            Have supervised 47 MSc and 16 PhD students.

 

            Current research projects:

 

Self Organizing Learning Array: Involves 1 PhD and 1 MS students. Described on the web page:

http://www.ent.ohiou.edu/~webcad/Current_Projects/solar/index.html

 

Machine Intelligence: Involves 4 PhD and 2 MS students.

http://www.ent.ohiou.edu/~starzyk/network/Research/NeuralNet/statement.html

 

 

WARSAW UNIVERSITY OF TECHNOLOGY ‑Institute of Electronics Fundamentals

Assistant Professor 1976-1983

 

Visiting Positions:

 

2009 NANYANG TECHNOLOGICAL UNIVERSITY – School of Computer Engineering, Visiting Professor

1994-2006 WRIGHT LABORATORIES - Automatic Target Recognition Group, AFOSR Summer Research Program

2002 MAGNOLIA BROADBAND; Senior Scientist

2001-2002 SARNOFF RESEARCH - Mixed Signal Design Group; Senior Design Engineer

1998-1999 WRIGHT LABORATORIES - Advanced Systems Research Group; IPA Fellow from AFOSR

1993 REDSTONE ARSENAL - U.S. Army Test, Measurement, and Diagnostic Activity; US Army Summer Research Program

1991 UNIVERSITY OF FLORENCE - Department of Electrical Engineering; Visiting Faculty

1990-1991 ATT BELL LABORATORIES - VLSI Systems Research Department; Visiting Faculty

1985-1995 NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY - Electricity Division; Summer research
1981-1983 McMASTER UNIVERSITY - Department of Electrical and Computer Engineering; Postdoctoral Fellow

International Research Collaboration:

 

NANYANG TECHNOLOGICAL UNIVERSITY, SINGAPORE – collaboration on embodied intelligence, vision and image processing, adaptive pattern recognition, speech and language understanding, cognitive information processing, self-organization of neural networks, associative learning, optimized reinforcement learning,.

INSTITUTO DALLE MOLLE DI STUDI SULL’INTELLIGENZA ARTIFICIALE, SWITZERLAND  – collaboration on universal artificial intelligence, hierarchical reinforcement learning, associative learning, rational agents, speech and language understanding, cognitive information processing, embodied intelligence.

INDIAN INSTITUTE OF TECHNOLOGY, DELHI, INDIA - collaboration on cognitive information processing, motivated learning in embodied intelligence, development of a sensory robot network and generation of goal-directed action outputs. 

INDIAN INSTITUTE OF TECHNOLOGY, BOMBAY, INDIA - collaboration on artificial intelligence, machine learning, intelligent processing and embedded real-time systems with emphasis on cognitive information processing, language understanding and motivated learning in embodied intelligence.

UNIVERSITE DE CAEN BASSE-NORMANDIE, FRANCE – collaboration on intelligent control architectures, probabilistic robotics, robot situation awareness.

STEVENS INSTITUTE OF TECHNOLOGY, HOBOKEN, NEW JERSEY, USA – collaboration on embodied intelligence with robotic applications, speech and language understanding, long term memory cells and sequential learning, decision making, cognitive information processing, adaptive control.

PORTLAND STATE UNIVERSITY, OREGON, USA – collaboration on robot vision, tracking, image matching, and obstacle avoidance, emotional humanoid robots, collaborative robots, integrated robot systems.

UNIVERSITY OF FLORENCE, ITALY - collaboration on neural networks and testing strategies.

McMASTER UNIVERSITY, CANADA - collaboration on computer aided design and mixed signal testing.

 

Consultant for: MAGNOLIA BROADBAND, SARNOFF RESEARCH, WRIGHT LABORATORIES, REDSTONE ARSENAL, ATT BELL LABORATORIES, MAGNETEK, NATIONAL INSTITUTE FOR STANDARDS AND TECHNOLOGY, SVERDRUP TECHNOLOGIES

 

SUMMARY OF ACCOMPLISHMENTS

 

My scholarly work had over 850 citations based on Google Scholar and over 200 citations on ISI Web of Knowledge Thompson Scientific. I published over 60 journal papers and book chapters and over 120 conference papers and developed 6 patents.

 

I was a PI on 21 research projects for US electronic industry, National Institute of Standards and Technology and Air Force Office of Scientific Research. I was also a recipient of 13 equipment grants for lab equipment and software for two labs I am in charge of at Ohio University – microelectronic design, and FPGA lab. Total value of these programs and grants is 3.8 mln US$.

 

I directed and was the major advisor of 47 MS thesis and 16 PhD dissertations. Eight of my graduates are professors at various universities in USA and abroad, two are chairmen of their departments, and five are working in American electronic industry (one of them was a division chief of a research lab. in the air force base). Two of my former students are industrial leaders and CEOs of their companies – one makes and sells electronic pacemakers to 115 countries in the world, and another one developed a software business and not his net worth is over 1 000 000 000 US$ (he now builds an industrial sea port in India). Currently, I supervise 7 PhD and 4 MS students (including 4 PhD students in Poland). 

 

For my good performance in teaching and research I was awarded four times by the dean of Electrical Engineering in Warsaw University of technology, twice I was awarded for outstanding research in the school of electrical engineering and computer science at Ohio University, and three times I was nominated for the Outstanding Graduate Faculty Award (only one such award is given each year at Ohio University). 

 

In 2005 my paper  "Self-Organizing Learning Array" published in IEEE Transaction on Neural Networks was nominated for Computational Intelligence Society Outstanding 2005 Paper Award, and my 2007  paper “Anticipation-Based Temporal Sequences Learning in Hierarchical Structure”, published in IEEE Transaction on Neural Networks received the best research paper award in the College of Engineering and Technology at Ohio University.

 

I have been nominated for IEEE Fellow at Circuits and Systems Society.

 

My other relevant experience can be summarized as follows:

·         The Keynote Speaker at the International Conference on Water, Environment, Energy and Society, paper How to Motivate Machines to Learn and Help Humans in Making Water Decisions? New Delhi, India, Jan. 12-16, 2009.

·         I was invited as a keynote speaker for the UNESCO strategic workshop, Integrated Modelling Approaches to Support Water Resource Decision Making: Crossing the Chasm, Paris, France, April 20-22, 2009.

 

TEACHING INTERESTS

 

Courses in Digital Design, Analog and Digital VLSI, Computer Aided Analysis, Digital Test and Testable Design, VHDL Hardware Description Language with FPGA Design, Machine Intelligence, General electrical engineering.

 

 

RESEARCH INTERESTS

 

Computational Intelligence, Self Organizing Learning Machines, Neural Networks, Automatic Target Recognition, VLSI and VHDL Systems Design, Dynamically Reconfigurable Design, Analog and Digital Testing, Computer-Aided Design.     

 

 

PUBLICATIONS       Over 190 Book Chapters, Refereed Journal and Conference Papers 

 

Chapters in books

 

  1. J. A. Starzyk, Motivated Learning for Computational Intelligence, in Computational Modeling and Simulation of Intellect: Current State and Future Perspectives, edited by B. Igelnik, IGI Publishing, 2010.

  2. J. A. Starzyk, Y. Liu, S. Batóg, „A Novel Optimization Algorithm Based on Reinforcement Learning”, to appear in `Computational Intelligence in Optimization-Applications and Implementations', Springer Verlag, 2009.

  3. J. A. Starzyk, "Motivation in Embodied Intelligence" in Frontiers in Robotics, Automation and Control, I-Tech Education and Publishing, Austria, 2008, pp. 83-110.  

  4. J. A. Starzyk, “Topological Analysis and Diagnosis of Analog Circuits”, Wydawnictwa Politechniki Slaskiej, 2008, 140 pp.

  5. J. A. Starzyk and A. El-Gamal, "Fault Location by Nodal Equations" in Analog Methods for Circuit Analysis and Diagnosis, edited by T. Ozawa, Marcel Dekker, Inc., New York, 1988.

  6. J. A. Starzyk, "Advances in Circuits and Systems - Selected Papers on Analog Fault Diagnosis", (co-author), IEEE Press, New York 1987.

  7. J. A. Starzyk, "Topological Analysis of Large Electronic Circuits", Prace Naukowe, Elektronika, No. 55, WPW, Warszawa, 1981, (in Polish), 184 pp.

  8. Co‑author of Polish translation "Computer‑aided analysis of electronic circuits, algorithms and computational techniques", by L.O. Chua and P.M. Lin, Wydawnictwa Naukowo‑Techniczne, Warszawa, 1981.

  9. "Introduction to Computer Design and Analysis of Electronic Networks", (Co‑author), Wydawnictwa PW, Warszawa, 1978 (in Polish).

 

Journal Papers

  1. J. A. Starzyk, J. T. Graham, and P. Raif, “Motivated Learning for Autonomous Robots Development”, IEEE Transactions on Autonomous Mental Development, submitted , 2010.

  2. J. A. Starzyk, H. He, “Spatio-Temporal Memories for Machine Learning: A Long-Term Memory Organization”, IEEE Trans. on Neural Networks, vol. 20, no. 5, May 2009, pp. 768 - 780.

     

  3. H. He, X. Shen, J. A. Starzyk, ”Power Quality Disturbances Analysis Based on EDMRA Method”, Int. Journal of Electrical Power & Energy Systems, vol. 31 (6), pp. 258-268, May 2009.

  4. Y. Liu, J. A. Starzyk, Z. Zhu, “Optimized Approximation Algorithm in Neural Network without Overfitting”, IEEE Trans. on Neural Networks, vol. 19, no. 4, June, 2008, pp. 983-995.

  5. H. F. A. Hamed, S. Kaya, J. A. Starzyk, “Use of nano-scale double-gate MOSFETs in low-power tunable current mode analog circuits” Analog Integrated Circuits and Signal Processing, Feb., 2008.

  6. J. A. Starzyk, and H. He, “Anticipation-Based Temporal Sequences Learning in Hierarchical Structure”, IEEE Trans. on Neural Networks, vol. 18,  no. 2,  March 2007, pp. 344 – 358. Received the best research paper award in the College of Engineering and Technology at Ohio University.

  7. J. A. Starzyk and H. He, “A Novel Low Power Logic Circuit Design Scheme,” IEEE Trans. Circuits Syst. II, vol. 54, no. 2, pp.176-180, Feb. 2007.

  8. Z. Zhu, F. van Graas and J. A. Starzyk, “GPS signal acquisition using the repeatability of successive code phase measurements” GPS Solutions, Springer, May 2007.

  9. S. Kaya, H. F. A. Hamed and J. A. Starzyk, “Low-Power Tunable Analog Circuit Blocks Based on Nanoscale Double-Gate MOSFETs,” IEEE Trans. Circuits Syst. II, vol. 54, no. 7, July 2007, pp. 571-575.

  10. J. A. Starzyk, H. He, and Y. Li, “A Hierarchical Self-organizing Associative Memory for Machine Learning”, Lecture Notes in Computer Science 4491: pp. 413-423, 2007.

  11. J. A. Starzyk, Y. Liu, D. Vogel, ”Sparse Coding in Sparse Winner Networks”, Lecture Notes in Computer Science 4492: pp. 534-541, 2007.

  12. Z. Zhu, H. He, J.A. Starzyk, and C. Tseng “Self-Organizing Learning Array and its Application to Economic and Financial Problems” Elsevier Science, Information Sciences, vol. 177, no 5, 1 March 2007, Pages 1180-1192.

  13. J. A. Starzyk, M. Ding, Y. Liu, ”Hybrid Pipeline Structure for Self-Organizing Learning Array”, Lecture Notes in Computer Science, 2007.

  14. H. He, and J. A. Starzyk, “Online Dynamic Value System for Machine Learning”, Lecture Notes in Computer Science 4491: pp. 441-448, 2007.

  15. J. A. Starzyk, Z. Zhu, and Y. Li, "Associative Learning in Hierarchical Self Organizing Learning Arrays“, IEEE Trans. Neural Networks, vol.17, no. 6, pp.1460-1470, Nov. 2006.

  16. H. He and J. A. Starzyk, "A Self Organizing Learning Array System for Power Quality Classification based on Wavelet Transform", IEEE Trans. on Power Delivery, Jan. 2006.

  17. J. A. Starzyk, Z. Zhu and T.-H. Liu "Self-Organizing Learning Array" IEEE Trans. on Neural Networks, vol. 16, no. 2, pp. 355-363, March 2005.  

  18. J. A. Starzyk, Z. Zhu, and Y. Li, "Associative Learning in Hierarchical Self Organizing Learning Arrays", Artificial Neural Networks: Biological Inspirations. Lecture Notes in Computer Science 3696: pp. 91-96, 2005.

  19. Janusz A. Starzyk, and Yue Li, David D. Vogel, "Neural Network with Memory and Cognitive Functions", Artificial Neural Networks: Biological Inspirations. Lecture Notes in Computer Science 3696: pp. 85-90, 2005.

  20. J. A. Starzyk, Dong Liu, Zhi-Hong Liu, D. Nelson, and J. Rutkowski, “Entropy-based optimum test points selection for analog fault dictionary techniques,” IEEE Transactions on Instrumentation and Measurement, vol. 53, no. 3, June 2004, pp. 754-761.

  21. J. A. Starzyk and F. Wang, "Dynamic Probability Estimator for Machine Learning" IEEE Trans. on Neural Networks, vol.15, no 2, March 2004, pp.298-308.  

  22. J. A. Starzyk, R. P. Mohn, and L. Jing, L., "A Cost-Effective Approach to the Design and Layout of a 14-b Current-Steering DAC Macrocell", IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, Vol. 51 ,  no. 1, Jan. 2004, pp. 196 - 200.

  23. D. E. Nelson, J. A. Starzyk, and D. D. Ensley, "Iterated wavelet transformation and signal discrimination for HRR radar target recognition",  IEEE Trans. on Systems, Man and Cybernetics, Part A  ,Vol. 33 , no.1 , Jan. 2003 , pp. 52 - 57.

  24. D. Liu and J. A. Starzyk, " A generalized fault diagnosis in dynamic analog circuits" Int. Journal of Circuit Theory and Applications, vol. 30, 2002, pp. 487-510.

  25. D. E. Nelson, J. A. Starzyk, and D. D. Ensley, "Iterative Wavelet Transformation and Signal Discrimination for HRR Radar Target Recognition," Multidimensional Systems and Signal Processing, Vol. 14, no.2. 2002.

  26. J. Becker, A. Alsolaim, M. Glesner, and J. Starzyk, “A Parallel Dynamically Reconfigurable Architecture for Flexible Aplication-Tailored Hardware/Software Systems in Future Mobile Communication”, The Journal of Supercomputing, Erratum Vol. 23, 132, 2002,  19(1): 105-127 (2001).

  27. J. Pang and J. A. Starzyk, "Fault Diagnosis in Mixed-Signal Low Testability System" An Int. Journal of Analog Integrated Circuits and Signal Processing, vol. 28, no.2, August 2001, pp. 159-170.

  28. J. A. Starzyk and Y.-W. Jan, and F. Qiu, "A DC-DC Charge Pump Based on Voltage Doublers", IEEE Trans. Circuits and Systems, Part I, vol. 48, no. 3, March 2001, pp. 350-359.

  29. G. N. Stenbakken, D. Liu J. A. Starzyk, and B. C. Waltrip, "Nonrandom Quatization Errors in Timebases", IEEE Trans. on Instrumentation and Measurement, vol. 50, no. 4, Aug. 2001, pp.888-892.

  30. J. A. Starzyk, D. E. Nelson, and K. Sturtz, " A Mathematical Foundation for Improved Reduct Generation in Information Systems", Journal of Knowledge and Information Systems, v. 2 n. 2, March 2000 p.131-146.

  31. J. A. Starzyk, J. Pang, S. Manetti, G. Fedi, and C. Piccirilli, "Finding Ambiguity Groups in Low Testability Analog Circuits", IEEE Trans. Circuits and Systems, Part I, vol 47, no. 8, 2000, pp. 1125-1137.

  32. G. Fedi, S. Manetti, J. A. Starzyk, M. C. Piccirilli "Determination of an Optimum Set of Testable Components in the Fault Diagnosis of Analog Circuits", IEEE Trans. Circuits and Systems, Part I, vol. 46, no.7, 1999, 779-787.

  33. J. A. Starzyk, D. E. Nelson, and K. Sturtz, "Reduct Generation in Information Systems", Bulletin of International Rough Set Society, 1999, 3 (1/2).

  34. J. A. Starzyk, "Hierarchical Analysis of High Frequency Interconnect Networks", IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol.13, no.5, 1994, pp. 658-664.

  35. J. A. Starzyk and X. Fang, "A CMOS Current Mode Winner-Take-All Circuit with both Excitatory and Inhibitory Feedback", Electronics Letters, 1993.

  36. G. N. Stenbakken and J. A. Starzyk, "Diakoptic and Large Change Sensitivity Analysis", IEE Proc. G, Circuits, Devices and Systems, vol. 139, no.1, 1992, pp.114-118.

  37. J. A. Starzyk and H. Dai, "A Decomposition Approach for Testing Large Analog Networks," Journal of Electronic Testing - Theory and Applications, no.3, 1992, pp. 181-195.

  38. J. A. Starzyk and A. Konczykowska, "Flowgraph Analysis of Large Electronic Networks", IEEE Trans. on Circuits and Systems, vol. CAS-33, 1986.

  39. J. A. Starzyk and E. Sliwa, "Upward Topological Analysis of Large Circuits Using Directed Graph Representation", IEEE Trans. on Circuits and Systems, vol. CAS-31, 1984, pp. 410-414.

  40. E. Salama, J. A. Starzyk and J. W. Bandler, "A Unified Decomposition Approach for Fault Location in Large Analog Circuits", IEEE Trans. on Circuits and Systems, vol. CAS-31, 1984, pp. 609-622.

  41. J. A. Starzyk, R. M. Biernacki and J. W. Bandler, "Evaluation of Faulty Elements within Linear Subnetworks", Int. Journal of Circuit Theory and Applications, vol. 12, 1984, pp. 23-37.

  42. J. A. Starzyk and J. W. Bandler, "Multiport Approach to Multiple-Fault Location in Analog Circuits", IEEE Trans. on Circuits and Systems, vol. CAS-30, 1983, pp. 762-765.

  43. J. A. Starzyk, "An Efficient Cluster Algorithm", Acta Polytechnica, CVUT, Praha, 1981, pp. 49-55.

  44. J. A. Starzyk, "Signal Flow-Graph Analysis by Decomposition Method", IEE Proc. on Electronic Circuits and Systems, No. 2, April 1980, pp. 81-86.

  45. G. Centkowski and J. A. Starzyk, "Topological Synthesis of LLF Networks", Acta Polytechnica, CVUT, Praha, 1980, pp. 77-86.

  46. J. A. Starzyk and E. Sliwa, "Hierarchic Decomposition Method for the Topological Analysis of Electronic Networks", Int. Journal of Circuit Theory and Applications, Vol. 8, 1980, pp. 407-417.

  47. J. A. Starzyk, "Generation of Complete Trees by the Method of Modified Structural Matrix", Arch. Elektrot., z.4, 1978, (in Polish), pp. 843-852.

  48. J. A. Starzyk, "New Method for Designing Complete Trees of a Pair of Conjugate Graphs", Arch. Elektrot., z.1, 1977, (in Polish), pp. 41-46.

  49. J. A. Starzyk, "Application of the Controlled Expansions Method to the Topological Analysis of Circuits", Arch. Elektrot., z.1, 1977, (in Polish), pp. 47-58.

  50. J. A. Starzyk, "Determination of the Nullator-Norator Graph's Complete Trees", Radio Electronics and Communication Systems, t.XX 12, 1977, (in Russian), pp. 9-15.

  51. J. A. Starzyk, and J. Wojciechowski, "Topological Analysis and Synthesis of Electrical Networks by the Method of Structural Numbers", Raport Naukowy IPE, Warszawa, 1977, (in Polish).

  52. J. A. Starzyk, "Topological Synthesis of Linear Active Networks Described by Multivariable Functions", Arch. Elektrot., z.2, 1976, (in Polish), pp. 287-295.

  53. J. A. Starzyk, "Topological Methods of Analysis of LSL Networks with Nullators and Norators", Prace Naukowe PW, Elektronika, No. 20, Warszawa, 1975, (in Polish), pp. 73-89.

  54. J. A. Starzyk, "Topological, Analysis of LSL Networks with Nullators and Norators; Impedance Dependencies", Prace Naukowe PW, Elektronika, No. 20, Warszawa, 1975, (in Polish), pp. 61-71.

  55. J. A. Starzyk, "Complement of Columns of Constant-row Structural Number to the Factorizable Number", Arch. Elektrot., z.2, 1975 (in Polish), pp. 237-244.

  56. Konczykowska and J. A. Starzyk "Determination of Structural Number of a Partitioned Graph. Part I and II.", Arch. Elektrot z.2, 1975, (in Polish), pp. 245-262.

 

Conference Papers

  1. J. A. Starzyk and D. Prasad, “Machine Consciousness: A Computational Model” Third International ICSC Symposium on Models of Consciousness, BICS 2010, Madrid, Spain, 14-16 July, 2010.

  2. J.A. Starzyk, P. Raif, and A.-H. Tan, “Mental Development and Representation Building through Motivated Learning” , WCCI 2010 - Special Session on Mental Architecture and Representation, Barcelona, Spain, July 18-23, 2010.

  3. W. Wang, B. Subagdja, A.-H. Tan, and J.A. Starzyk, “A Self-Organizing Approach to Episodic Memory Modeling”, The 2010 IEEE World Congress on Computational Intelligence, Barcelona, Spain, July 18-23, 2010.

  4. V. A. Nguyen, J. A. Starzyk, A. L. P. Tay and W. B. Goh, “Spatio-Temporal Sequence Learning of Visual Place Cells for Robotic Navigation”, The 2010 IEEE World Congress on Computational Intelligence, Barcelona, Spain, July 18-23, 2010.

  5. J. A. Starzyk, P. Raif, A.-H. Tan, “Motivated Learning as an Extension of Reinforcement Learning”, 4th International Conference on Cognitive Systems, ETH Zurich, Switzerland, Jan. 27-28, 2010.

  6. J. A. Starzyk, P. Raif, A.-H. Tan, “Motivated Learning as an Extension of Reinforcement Learning”, 4th International Conference on Cognitive Systems, ETH Zurich, Switzerland, Jan. 27-28, 2010.

  7. J.A. Starzyk, “Water Resource Planning and Management using Motivated Machine Learning”, 10th Kovacs Colloquium UNESCO, Hydrocomplexity: New Tools for Solving Wicked Water, Paris, France, 2-3 July 2010.

  8. J. A. Starzyk and Basawaraj,  “Self Organizing Neural Network for Question Answering“ Thirteenth  International Conference on Cognitive and Neural Systems (ICCNS), Boston University, May 27-30, 2009.

  9. J. A. Starzyk and J. Graham “A Goal Creation System With Curiosity” Thirteenth  International Conference on Cognitive and Neural Systems (ICCNS), Boston University, May 27-30, 2009.

  10. J. A. Starzyk, Xinming Yu, “Correlation-based neural network for active vision” Thirteenth  International Conference on Cognitive and Neural Systems (ICCNS), Boston University, May 27-30, 2009.

  11. J. A. Starzyk, P. Raif, “Motivated Learning Based On Goal Creation in Cognitive Systems” Thirteenth  International Conference on Cognitive and Neural Systems (ICCNS), Boston University, May 27-30, 2009.

  12. J.A. Starzyk, “Motivated Machine Learning for Water Resource Management”, Workshop on Integrated Modelling Approaches to Support Water Resource Decision Making: Crossing the Chasm, UNESCO-Paris, 20-21 April 2009.

  13. F.A. Elmisery, and J.A. Starzyk, “A neural network based on sequence learning for speech recognition”  ICCES 2008. International Conference on Computer Engineering & Systems, Cairo, Egypt,  25-27 Nov. 2008 pp. 139 – 142.

  14. J. A. Starzyk and Basawaraj,  “Hierarchical Neural Network for Text Based Learning”, Twelfth International Conference on Cognitive and Neural Systems (ICCNS), Boston University, May 14-17, 2008.

  15. J. Graham and J. A. Starzyk, “Self-Organizing Hierarchical Neural Network with Correlation Based Sparse Connections”, Twelfth International Conference on Cognitive and Neural Systems (ICCNS), Boston University, May 14-17, 2008.

  16. J. A. Starzyk, Yinyin Liu, “Attention aided perception in sparse-coding networks”, Twelfth International Conference on Cognitive and Neural Systems (ICCNS), Boston University, May 14-17, 2008.

  17. J. A. Starzyk, Xinming Yu, “Active vision system for embodied intelligence based on retina sampling model”, Twelfth International Conference on Cognitive and Neural Systems (ICCNS), Boston University, May 14-17, 2008.

  18. J. Graham and J. A. Starzyk, “A Hybrid Self-organizing Neural Gas Based Network”, IEEE World Congress on Computational Intelligence, Hong Kong, June 2008.

  19. H. He, S. Chen, . Y. Cao, and  J. A. Starzyk, “Incremental Learning for Machine Intelligence”, Twelfth International Conference on Cognitive and Neural Systems (ICCNS), Boston University, May 14-17, 2008.

  20. Y. Liu, J. A. Starzyk, and Z. Zhu, “Optimizing number of hidden neurons in neural networks”, Proc. Int. Conf. Artificial Intelligence and Applications, AIA’2007, Innsbruck, Austria, Feb. 12 – 14, 2007.

  21. J. A. Starzyk, Y. Liu, “Hierarchical spatio-temporal memory for machine learning based on laminar minicolumn structure,” Eleventh International Conf. on Cognitive and Neural Systems, Boston University, May 16-19, 2007.

  22. J.A.Starzyk, Yinyin Liu, and Haibo He, “Challenges of Embodied Intelligence”, Proc. Int. Conf. on Signals and Electronic Systems, ICSES'06, Lodz, Poland, Sep. 17-20, 2006.

  23. S. Kaya, H. Hamed and J. A. Starzyk, “Low-Power Tuneable Analog Circuit Blocks Based on Nanoscale Dual-Gate MOSFETs”, 6th IEEE Conf. on Nanotechnology – IEEE Nano 2006, 16-20 July, 2006, Cincinnati, OH, USA.

  24. S. Kaya, H. Hamed and J. A. Starzyk, “Compact Tunable Current-Mode Analog Circuits Using DGMOSFETs”, IEEE Int. SOI Conf. Oct. 2–5, 2006, Niagara Falls, NY.

  25. J.A.Starzyk, Mingwei Ding, Haibo He, "Optimized Interconnections in Probabilistic Self-Organizing Learning", Proc. IASTED Int. Conf. on Artificial Intelligence and Applications, Innsbruck, Austria, Feb. 14-16, 2005.

  26. J. A. Starzyk,Y. Guo, and Z. Zhu, ”Dynamically Reconfigurable Neuron Architecture for the Implementation of Self-Organizing Learning Array”, Proc. 18th Int. Parallel and Distributed Processing Symposium, Santa Fe, New Mexico, April 26– 30, 2004.

  27. H. He, J. A. Starzyk, "DesignPower Quality Disturbances Analysis based on Wavelet Multiresolution Decomposition", American Mathematical Society (AMS) Conf., Ohio University, Athens, OH, March 26-27, 2004.

  28. J. A. Starzyk, Y. Guo, Z. Zhu, “SOLAR and its hardware development",  Proc. Computational Intelligence and Natural Computing, 2003 (CINC’03),  2003, Cary, North Carolina USA , Sept. 26-30, 2003.

  29. J. A. Starzyk, Zhen Zhu, H. He and Zhineng Zhu, "Self-Organizing Learning Array and Its Application to Economic and Financial Problems, "Proc.  Joint Conference on Information Systems, 2003, Cary, North Carolina USA, Sept. 26-30, 2003.

  30. J. A. Starzyk and T.-H. Liu, “Design of a Self-Organizing Learning Array System”, Proc. IEEE Int. Symposium on Circuits and Systems, May 26-29, Bangkok, Thailand, 2003.

  31. J. A. Starzyk and R. Mohn, “Cost-Oriented Design of a 14-bit Current Steering DAC Macrocell”, Proc. IEEE Int. Symposium on Circuits and Systems, May 26-29, Bangkok, Thailand, 2003.

  32. Alaqeeli, J. A. Starzyk, F. van Graas, “Real Time Acquisition and Tracking for GPS Receiver”, Proc. IEEE Int. Symposium on Circuits and Systems, May 26-29, Bangkok, Thailand, 2003.

  33. J. A. Starzyk, and Y. Guo, “Dynamically Self-Reconfigurable Machine Learning Structure for FPGA Implementation” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)  Las Vegas, Nevada, USA, June 23 - 26, 2003.

  34. J. Pang and J.A. Starzyk, ”Fast Direct GPS Signal Acquisition Using FPGA”, Proc. (Krakow, Poland, 2003).

  35. J. A. Starzyk, and Y. Guo, “A Self-Organizing Learning Array and its Hardware-Software Co-Simulation”, Proc. ECCTD, (Krakow, Poland, 2003).

  36. J. A. Starzyk and D. Liu, "A Decomposition Method for Analog Fault Location", IEEE Int. Symposium on Circuits and Systems, May 26-29, Scottsdale, Arizona, 2002.

  37. J. A. Starzyk and D. Liu, "Locating Stuck-at Faults in Analog Circuits", IEEE Int. Symposium on Circuits and Systems, May 26-29, Scottsdale, Arizona, 2002.

  38. J. Starzyk and Z. Zhu, "Software Simulation of a Self-Organizing Learning Array System", The 6th IASTED Int. Conf. Artificial Intelligence & Soft Comp.(ASC 2002), July 17-19, 2002, Banff, Alberta, Canada.

  39. J. Pang, J. A. Starzyk, "P-code Generator FPGA Design for Direct GPS P(Y)-Code Acquisition", 12th International Conference on Field Programmable Logic and Applications (FPLA), 2002.

  40. M. Ding, A. Alsolaim, and J. Starzyk, "Designing and Mapping of a Turbo Decoder for 3G Mobile Systems Using Dynamically Reconfigurable Architecture " Engineering of Reconfigurable Systems and Algorithms, ERSA'02, The Int. Multi Conference in Computer Science, June 24-27, Las Vegas, Nevada, 2002.

  41. J. A. Starzyk Y. Guo, "A Self Organized Classifier Based on Maximum Information Index and its Develpoment Using VHDL", 2002 IEEE Int. Symposium on Intelligent Signal Processing and Communication Systems, 21-24 November 2002, Kaohsiung, Taiwan, R.O.C. 2002.

  42. J.A. Starzyk and D. Liu, "A new approach to multiple fault diagnosis in linear analog circuits," Proceeding of the 7th IEEE International Mixed Signal Testing Workshop (IMSTW), Atlanta, GA, Jun. 2001.

  43. J. A. Starzyk* and D. Liu, "A Method for Multiple Fault Diagnosis in Analog Circuits" Proc. Southeastern Symposium on System Theory, (Athens, OH, 18-20, March 2001),   pp. 65 - 68

  44. J. A. Starzyk and L. Jing, "Analog Circuits for Self Organizing Neural Networks Based on Mutual Information" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001).

  45. Y. Zeng and J. A. Starzyk, "Statistical Approach for Clustering in Pattern Recognition" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001).

  46. Alaqeeli and J. A. Starzyk, "Hardware Implementation of Fast Convolution for GPS Signal Acquisition Using FPGA" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001).

  47. Alsolaim and J. A. Starzyk, "Dynamically Reconfigurable Solution in the Digital Baseband Processing for Future Mobile Radio Devices" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001).

  48. D. E. Nelson and J. A. Starzyk, "High Range Resolution Radar Signal Classification: A Partitioned Rough Set Approach" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001).

  49. J. A. Starzyk and Y. Guo, "An Entropy-based Learning Hardware Organization Using FPGA" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001).

  50. J. A. Starzyk and D. Liu, "Multiple Fault Diagnosis of Analog Circuits Based on Large Change Sensitivity Analysis" Proc. ECCTD, (Espoo, Finland, Aug. 2001).

  51. D. E. Nelson and J. A. Starzyk, "High Range Resolution Radar - Extensions to Rough Set Theory for Automatic Target Recognition", SPIE 15th Annual Int. Symp. on Aerospace/Defense Sensing Simulation and Controls, (Orlando FL, April 2001) Best Paper award.

  52. J. A. Starzyk and D. Liu, "Multiple Fault Diagnosis of Analog Circuits by Locating Ambiguity Groups in Test Equation", Proc. IEEE Int. Symp. Circuits and Systems (Sydney, Australia, 2001). 6-9 May 2001, pp. 199 - 202 vol. 5

  53. J. A. Starzyk and Z. Zhu, "Averaging Correlation for C/A Code Acquisition and Tracking in Frequency Domain", Proc. Midwest Symp. on Circuits and Systems (Dayton, OH, Aug. 2001).

  54. J. A. Starzyk and Y. Guo, "Reconfigurable Self-Organizing NN Design Using Virtex FPGA", Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (Las Vegas, NV, June 2001).

  55. X. S. Song and J. A. Starzyk, "Feature Selection using Mutual Information and Statistical Techniques", Proc. 2001 IEEE Military Communications Conf. (MILCOM’2001), Washington D.C, October 2001.

  56. Zhou Q., Chelberg, D., Zeng Y., and Starzyk, J. “Robust Optical Flow Estimation Using Invariant Feature”, Proc. Southeastern Symp. on System Theory, (Athens, OH, 2001),  Mar 2001,  pp. 263 – 267.

  57. Alsolaim, J. Becker, M. Glesner, and J. Starzyk, "A Dynamically Reconfigurable System-on-a chip Architecture for Future Mobile Digital Signal Processing", The European Signal Processing Conference EUSIPCO, (Sept. 5 - 8, 2000, Tampere, Finland).

  58. J. Becker, M. Glesner, A. Alsolaim, J. Starzyk, "Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures", the 2000 Int. Conf. on Parallel and Distributed Processing Techniques and Apllications, (Las Vegas, NV, June 2000).

  59. Alsolaim, J. Becker, M. Glesner, J. Starzyk. "Dynamically Reconfigurable Array Architecture for Future Mobile Digital Baseband Processing." 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), April 16-19, 2000, Napa Valley, California.

  60. Y. Zeng and J. Starzyk, "Piecewise Linear Approach: a New Approach in Automatic Target Recognition," SPIE 14th Annual Int. Symp. on Aerospace/Defense Sensing Simulation and Controls, (Orlando FL, April 2000).

  61. J. Starzyk, J. Pang, "Fault Diagnosis in Analog and Mixed Mode Low Testability Systems", Proc. IEEE Int. Symp. Circuits and Systems (Geneva, Switzerland, 2000).

  62. D. E. Nelson and J. A. Starzyk "Fusing Marginal Reducts for HRR Target Identification" 4th World Multi-Conference on Systems, Cybernetics and Informatics (SCI2000), (Orlando, Florida, July 2000), pp. 452-460 Best Paper award.

  63. G. N. Stenbakken, D. Liu J. Starzyk, and B. C. Waltrip, "Nonrandom Quatization Errors in Timebases", Proc. IEEE Instrumentation and Measurement Technology Conference (Baltimore, MD May 2000).

  64. J. Starzyk and J. Pang, "Evolvable Binary Artificial Neural Network for Data Classification", the 2000 Int. Conf. on Parallel and Distributed Processing Techniques and Apllications, (Las Vegas, NV, June 2000).

  65. F. Qiu, J. A. Starzyk and Y.-W. Jan, "Analog VLSI Design of Multi-phase Voltage Doublers with Frequency Regulation", the 1999 Southwest Symposium on Mixed-Signal Design, (Tucson, AZ, April, 1999).

  66. J. A. Starzyk and Y.-W. Jan," A Simulation Program Emphasized on DC Analysis of VLSI Circuits: SAMOC", the 1999 Southwest Symposium on Mixed-Signal Design, (Tucson, AZ, April, 1999).

  67. G. N. Stenbakken, D. Liu, J. A. Starzyk and B. C. Waltrip, "A new method to compensate quantized time-base nonlinearity of sampling instruments," Workshop on Software Embedded Systems Testing (WSEST), National Institute of Standards and Technology, Gaithersburg, MD, Nov. 1999.

  68. V. Brygilevicz, J. Wojciechowski, and J. A. Starzyk, "Testing of Analog Dynamic Systems Based on Integral Sensisitivity", Proc. ECCTD, (Stresa, Italy, Aug. 1999).

  69. J.A. Starzyk, J. Pang, G. Fedi, R. Giomi, S. Manetti, "A Software Program for Ambiguity Group Determination in Low Testability Analog Circuits", Proc. ECCTD, (Stresa, Italy, Aug. 1999).

  70. R. Morawski, B. Manhire, and J. Starzyk, "Engineering Education in Poland", ASEE Conf., Seattle, June, 1998.

  71. J. A. Starzyk, D. E. Nelson, and K. Sturtz, "Reduct Generation in Information Systems", The Sixth Int. Workshop on Rough Sets, Data Mining and Granular Computing, at JCIS'98, (Research Triangle Park, NC), Oct. 1998.

  72. D. E. Nelson and J. A. Starzyk, "Advanced Feature Selection Methodology for Automatic Target Recognition", Proc. Southeastern Symposium on System Theory, (Coolville, TN, 1997).

  73. Z-H. Liu and J. A. Starzyk, "Mixed Signal Testing of Analog Components on Printed Circuit Boards", Proc. Midwest Symp. on Circuits and Systems (Sacramento, CA, 1997).

  74. J. A. Starzyk and J. Zou, "Direct Symbolic Analysis of Analog Networks", Proc. Midwest Symp. on Circuits and Systems (Ames, Iowa, 1996).

  75. J. A. Starzyk and Ying-Wei Jan, "A Voltage Based Winner Takes All Circuit for Analog Neural Networks", Proc. Midwest Symp. on Circuits and Systems (Ames, Iowa, 1996).

  76. J. A. Starzyk and D. Nelson, "Independent Classifiers in Ontogenic Neural Networks for ATR", Adaptive Distributed Parallel Computing Symposium (Fairborn, OH, 1996).

  77. J. A. Starzyk and S. Chai, "Object representation using Fourier descriptors in pattern classification", Proc. Artificial Neural Networks in Engineering Conf. (St. Louis, MO, 1995).

  78. J. A. Starzyk and Ying-Wei Jan, "Low Power Voltage Based Winner Takes All Circuit for Analog Neural Networks", OAI Neural Network Symposium, (Athens, OH, 1995).

  79. J. A. Starzyk and Xingyuan Lee, "Rapid Object Identification Based on Fourier Descriptors", OAI Neural Network Symposium, (Athens, OH, 1995).

  80. X. Fang and J. A. Starzyk, "VLSI design of neural network based image processor", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

  81. J. A. Starzyk and Y-W. Jan, "Algorithm and architecture for feature extraction in image processong", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

  82. J. A. Starzyk and S. Chai, "Supervised learning with potentials for neural network- based object recognition", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

  83. J. A. Starzyk and C-H. Chen, "A VLSI inner-product processor for real-time DSP applications", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

  84. J. A. Starzyk and M. SenthilKumar, "Partial arithmetic - algorithms and architecture", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

  85. J. A. Starzyk, Z. H. Liu, and J. Zou, "An organization of the test bus for analog and mixed-signal systems", Proc. of IEEE VLSI Test Symposium, (Cherry Hill, N.J. 1994).

  86. X. Fang and J. Starzyk, "A novel winner-take-all circuit", the World Conf. on Neural Networks, (Portland, OR, 1993).

  87. J. A. Starzyk and J. Zou, "On-line error detection in analog and mixed-signal systems", IEEE Int. Test Conference, (Baltimore, MD, 1993).

  88. J. A. Starzyk and X. Fang, "System level design of a complex neural network for target recognition", IEEE Int. Conf. on Neural Network Applications to Signal Processing, (Singapore, 1993).

  89. J. A. Starzyk and C.-H. Chen, "A VLSI Inner Product Processor with Built-in Self Test for Real Time DSP Applications", Int. Conf. on Signal Proc. Applications and Technology, (Santa Clara, CA, 1993).

  90. J. A. Starzyk and C. H. Chen, "A One Dimensional Processor Array for LU Decomposition", Proc. IEEE Int. Workshop on Intelligent Signal Processing and Communication Syst. (Taipei, Taiwan, ROC, 1992).

  91. J. A. Starzyk and N. Ansari, "Feedforward Neural Network for Handwritten Character Recognition", Proc. IEEE Int. Symp. Circuits and Systems (San Diego, CA, 1992).

  92. J. A. Starzyk and H. Dai, "Noninvasive Voltage Measurement Through an On-Chip Test Structure", Proc. IEEE Int. Test Conference (Baltimore, MD, 1992).

  93. J. A. Starzyk and S.K. Chai, "Vector Contour Representation for Object Recognition in Neural Networks", IEEE Int. Conf. Systems, Man, and Cybernetics, (Chicago, IL, 1992).

  94. J. A. Starzyk and N. Ansari, "Distance Field Approach to Handwritten Character Recognition", Proc. Fifth Conf. on Neural Networks and Parallel Distributed Processing, (Fort Wayne, IN, 1992).

  95. J. A. Starzyk and H. Dai, "Automated Testing Using Circuit Decomposition", Proc. IEEE Instr. Measurement Technology Conf. (Atlanta, GA, 1991).

  96. J. A. Starzyk and X. Wu, "Approximation Using Linear Fitting Neural Network", Proc. Artificial Neural Networks in Engineering Conf. (St. Louis, MO, 1991).

  97. J. A. Starzyk, "Neural Networks in Analog Fault Diagnosis", VII Riunione Annuale Dei Ricercatori, (Trani, Italy, 1991).

  98. J. A. Starzyk and H. Dai, "A Decomposition Approach for Parameter Identification in Large Scale Networks," Proc. IEEE Int. Symp. Circuits and Systems (New Orleans, LA, 1990).

  99. J. A. Starzyk and M. El-Gamal, "Artificial Neural Network for Testing Analog Circuits", Proc. IEEE Int. Symp. Circuits and Systems (New Orleans, LA, 1990).

  100. J. A. Starzyk and M. Eshghi, "Highly Parallel Adaptive Filter," Proc. IEEE Int. Symp. Circuits and Systems (Portland, OR, 1989).

  101. J. A. Starzyk and E. Sliwa, "Tolerances in Symbolic Network Analysis," Proc. IEEE Int. Symp. Circuits and Systems (Portland, OR, 1989) - invited paper.

  102. J. A. Starzyk and H. Dai, "Time Domain Testing of Large Nonlinear Circuits," Proc. European Conf. Circuit Theory and Design, (Brighton, United Kingdom, 1989).

  103. J. A. Starzyk and H. Dai, "Sensitivity Based Testing of Nonlinear Dynamic Circuits", Proc. IEEE Int. Symp. Circuits and Systems (Espoo, Finland, 1988).

  104. J. A. Starzyk and M. A. El-Gamal, "Diagnosability of Analog Circuits a Graph Theoretical Approach", Proc. IEEE Int. Symp. Circuits and Systems (Espoo, Finland, 1988).

  105. J. A. Starzyk and H. Dai, "Fault Diagnosis and Calibration of Large Analog Circuits", Proc. IEEE Int. Symp. Circuits and Systems (Espoo, Finland, 1988).

  106. J. A. Starzyk and M. El-Gamal, "Fault Diagnosis of Nonlinear Resistive Circuits", Proc. 31st Midwest Symp. on Circuits and Systems (St. Louis, MO, 1988).

  107. J. A. Starzyk and H. Dai, "Multifrequency Measurement of Testability in Analog Circuits", Proc. IEEE Int. Symp. Circuits and Systems (Philadelphia, PA, 1987).

  108. J. A. Starzyk and M. A. El-Gamal, "An Optimization Approach to Fault Location in Analog Circuits", Proc. European Conf. Circuit Theory and Design (Prague, 1985).

  109. J. A. Starzyk and V.S.R. Dandu, "Overlapped Multi-Bit Scanning Multiplier", Proc. IE: VLSI in Computers (Port Chester, NY, 1985).

  110. J. A. Starzyk and H. Dai, "Element Evaluation in the Resistive Networks", Proc. 28th Midwest Symp. on Circuits and Systems (Louisville, Kentucky, 1985).

  111. J. A. Starzyk and S. C. Rastogi, "Hierarchical Decomposition Approach to D.C. Power Flow Solution", Proc. 28th Midwest Symp. on Circuits and Systems (Louisville, Kentucky, 1985).

  112. J. A. Starzyk and M. A. El-Gamal, "Topological Conditions for Element Evaluation", Proc. 28th Midwest Symp. on Circuits and Systems (Louisville, Kentucky, 1985).

  113. J. A. Starzyk, "Decomposition Approach to a VLSI Symbolic Layout with Mixed Constraints", Proc. IEEE Int. Symp. Circuits and Systems (Montreal, 1984). pp. 457-460.

  114. J. A. Starzyk and J. W. Bandler, "Design of Tests for Parameter Evaluation within Remote Inaccessible Faulty Subnetworks", Proc. IEEE Int. Symp. Circuits and Systems (Newport Beach, CA, 1983), pp. 1106-1109.

  115. E. Salama, J. A. Starzyk and J. W. Bandler, "A Unified Decomposition Approach for Fault Location in Large Analog Circuits", Proc. European Conf. Circuit Theory and Design (Stuttgart, 1983).

  116. J. A. Starzyk and J. W. Bandler, "Nodal Approach to Multiple-Fault Location in Analog Circuits", Proc. IEEE Int. Symp. Circuits and Systems (Rome, 1982), pp. 1136-1139.

  117. J. W. Bandler, R. M. Biernacki, A. E. Salama and J. A. Starzyk, "Fault Isolation in Linear Analog Circuits Using the Ll Norm", Proc. IEEE Int. Symp. Circuits and Systems (Rome, 1982), pp. 1140-1143.

  118. H. Gupta, J. W. Bandler, J. A. Starzyk and J. Sharma, "A Hierarchical Decomposition Approach for Network Analysis", Proc. IEEE Int. Symp. Circuits and Systems (Rome, 1982), pp. 643-646.

  119. R. M. Biernacki and J. A. Starzyk, "A Test Generation Algorithm for Parameter Identification of Analog Circuits", Proc. European Conf. Circuit Theory and Design, (The Hague, 1981), pp. 993-997.

  120. G. Centkowski, J. A. Starzyk and E. Sliwa, "Symbolic Analysis of Large LLS Networks by Means of Upward Hierarchical Analysis", Proc. European Conf. Circuit Theory and Design (The Hague, 1981), pp. 358-361.

  121. Konczykowska and J. A. Starzyk, "Computer Justification of Upward Topological Analysis of Signal-Flow Graphs", Proc. European Conf. Circuit Theory and Design, (The Hague, 1981), pp. 464-467.

  122. G. Centkowski, J. A. Starzyk and E. Sliwa, "Computer Implementation of Topological Methods in the Analysis of Large Networks", Proc. European Conf. Circuit Theory and Design (Warsaw, 1980), pp. 69-74.

  123. Konczykowska and J. A. Starzyk, "Computer Analysis of Large Signal Flowgraphs by Hierarchical Decomposition Method", Proc. European Conf. Circuit Theory and Design (Warsaw, 1980), pp. 408-413.

  124. R. M. Biernacki and J. A. Starzyk, "Sufficient Test Conditions for Parameter Identification of Analog Circuits Based on Voltage Measurements", Proc. European Conf. Circuit Theory and Design (Warsaw, 1980), pp. 233-241.

  125. J. A. Starzyk, "An Efficient Cluster Algorithm", Proc. of 5th Czech-Polish Workshop on Circuit Theory (Podbierady, 1980).

  126. J. A. Starzyk and E. Sliwa, "Topological Analysis by Hierarchic Decomposition Method", Fourth Int. Symp. on Network Theory (Ljubljana, 1979), pp. 155-160.

  127. J. A. Starzyk and A. Konczykowska, "Hierarchical Decomposition of Signal-Flow Graphs", Third Int. Conf. Electronic Circuits (Prague, 1979), pp. 248-251.

  128. J. A. Starzyk, "Advanced Topological Analysis", Proc. of 4th Polish-Czech Workshop on Circuit Theory (Bocheniec, 1979), pp. 90-94.

  129. J. A. Starzyk, "The Distor Graphs", Proc. of 3rd Czech-Polish Workshop on Circuit Theory (Prenet, 1978).

  130. J. A. Starzyk, "Topological Synthesis of Linear Network with Grounded Operational Amplifiers", Proc. of 2nd Polish-Czech Workshop on Circuit Theory (Czarlino, 1977), pp. 201-206.

  131. J. A. Starzyk, "Edge Orientation in Topological Synthesis of Linear Networks", Fifth Symp. Mathematical Methods in Electrical Engineering, (Podlesice, 1976), (in Polish), pp. 169-179.

  132. J. A. Starzyk, "Selected Topics in Topological Synthesis of Networks by the Method of Structural Numbers", Symp. for XXV Anniversary of Electrical Engineering Dept. (Warsaw, 1976), (in Polish), pp. 116-117.

  133. J. A. Starzyk, "Topological Synthesis of Linear Active Networks with the Method of Structural Numbers", Proc. European Conf. Circuit Theory and Design (Genova, 1976), pp. 340-348.

  134. J. A. Starzyk, "Problems in Topological Analysis", First National Conf. URSI (Warsaw, 1975), (in Polish), pp. 250-252.

  135. J. A. Starzyk, "Topological Synthesis of Multivariable Network Functions", Third Int. Symp. on Network Theory (Split, 1975), pp. 555-564.

  136. J. A. Starzyk, "Complement of Set of Trees", Eight Asilomar Conf. Circuits, Systems and Computers, (Pacific Grove), 1974, pp. 227-230.

 

PATENTS

           

·         Janusz A. Starzyk, "Dynamic Probability Estimator for Self-Organizing Data-Driven Learning Hardware", Ohio University, Provisional Patent Application, prepared in February 2003.

 

·         Janusz A. Starzyk, "Self-Organizing Data-Driven Learning Hardware with Local Interconnections", Ohio University, US Patent Application, Serial # 10/174,038, filed on June 18, 2002, United States Patent Serial # 7,293,002 B2, awarded Nov. 6, 2007.

 

·         Janusz A. Starzyk, Russell Mohn, Thomas Senko, "Algorithm for the Reduction of Systematic Errors in Current Steering DAC", Sarnoff Corp., US Patent Application, Serial No.:  395690, Filed:  March 24, 2003, United States Patent 20030227402.

 

·         Janusz A. Starzyk and Dale E. Nelson, "Object Identification System and Method", Ohio University, PCT/US01/22852, PCT Filed: July 20, 2001, PCT Pub. No.: WO02/09026, PCT Pub. Date.: January 31, 2002, International Patent Serial # 7,035,754, awarded April 25, 2006.

 

·         Janusz A. Starzyk, “Method and System of Goal Creation for Machine Intelligence”, Air Force Research Lab., Provisional Patent Application, prepared in August 2006.

 

·         Janusz A. Starzyk and Dale E. Nelson, "System and method for identifying an object ", Ohio University, Appl. No.:11/361,595, PCT Filed: February 24, 2006, International Patent Serial # 7,308,378, awarded December 11, 2007.

 

 

Invited talks (since 1991):

 

Ø      Seminar, “Hierarchical Analysis of VLSI Interconnect,” AT&T Bell Labs, Dr. B. Ackland, VLSI Systems Group, 1991.

 

Ø     The Keynote Speaker at the VII Riunione Annuale Dei Ricercatori, Trani, Italy, 1991.

 

Ø     Seminar, “Neural Networks for Analog Testing and Approximation”, University of Florence, Italy          Dr. Liberatore, 1991.

 

Ø      Seminar, “Artificial Neural Vision Learning System” Institute of Electronic Systems, Warsaw Technical University, 1992.

 

Ø      Seminar, “Hardware Implementation of ANVIL Algorithms”, Wright-Patterson, Dr. Nelson, AFB, Dayton, OH, 1992.

 

Ø     Seminar, “Embeded Diagnostics and Built-in Test”, U.S. Army Research Office, Dr. Li-Pi Su, Readstone Arsenal, AL, 1993.

 

Ø     Invited talk, “On-line Error Detection in Analog Systems”, Ford Electronics, Dr. G. Moszynski, Detroit, MI, 1993.

 

Ø     Panel presentation, “Analog Boundary Scan Cell for Mixed-Signal Testing”, IEEE Working Group P1149.4, Dr. M. Soma, Baltimore, MD, 1993.

 

Ø      Invited talk, “Analog Boundary Scan Cell”, Ford Electronics, Dr. S. Stoica, Detroit, MI, 1994.

 

Ø      Seminar, “Neural Networks for Image Recognition”, Institute of Electronic Systems, Warsaw Technical University, Warsaw, Poland, August 1994.

 

Ø      Invited talk, “Testing of Analog Interconnections”, Ford Electronics, Dr. S. Stoica, Detroit, MI, 1995.

 

Ø      Seminar, “Information Based Feature Selection”, Wright Labs, Dayton, OH, 1996.

 

Ø      Seminar, “Switch Level MOS Transistor Model for Analog Simulation”, OSU, Columbus, OH, 1996.         

 

Ø      Invited talk, “Mixed signal testing and design for testability” Ford Electronics, Detroit, MI, Jan. 1997.

 

Ø      Seminar, “Iterative wavelet transform in NN learning”, Warsaw University of Technology, Warsaw, Poland, June 1997.

 

Ø      Invited talk, “Manufacturing test in IC fabrication of automotive electronics” Delco Electronics, Kokomo, IN, Sept. 1997.

 

Ø      Invited lecture, “Feature Selection in self‑organized learning for target recognition”, Technical University of Darmstadt, Darmstadt, Germany, Dec. 1998.

 

Ø      Seminar, "Signal Clustering in Target Recognition", Wright Labs., Dayton, OH, 1998.

 

Ø      Panelist on the Workshop on the Software Embedded System Test, Gaithersburg, MD, Nov. 7-11, 1999.

 

Ø      Seminar, "Hybrid Distance and Piecewise Linear Approximation for SAR/HRR Target Identification", Wright Labs., Dayton, OH, 1999.

 

Ø      The Keynote Speaker at the System on a chip and Reconfigurable Computing Workshop, Riyadh, Saudi Arabia, 1999.

 

Ø      Gave two seminar presentations in Magnolia Broadband, Clinton NJ, on VCO and PLL design for their design engineers. Summer, 2002.

 

Ø      Technical design presentation, “Design of 14 bit DAC in 0.13um CMOS”, Terayon Corp. (San Jose California), March, 2002.

 

Ø      Seminar, “Collaborative Sensing and Threat Awareness in Urban Operation - Machine Intelligence Approach”, AFRL/SNAT WPAFB, August 2005.

 

Ø      Seminar, “Machine Intelligence Approach to Sensing and Vigilance”, AFRL/SNAT WPAFB, August 2006.

 

Ø      The Keynote Speaker at the The International Conference on Signals and Electronic Systems, ICSES'06, Lodz, Poland, Sep. 17-20, 2006.

 

Ø      Seminar “Challenges of the embodied intelligence”, Institute of Electronic Systems, Warsaw University of Technology, Sept. 2006.

 

Ø      The Keynote Speaker at the International Conference on Artificial Intelligence, Siedlce, Poland, Sept. 21-22, 2006.

 

Ø      Seminar, “Goal Creation System for Machine Intelligence”, HEIDI group, Ohio University, October 2006.

 

Ø      Invited lecture, “Embodied Intelligence”, Department of Electrical Engineering and Computer Science, at Silesian University of Technology, Gliwice, Poland, Oct. 2007.

 

Ø      The Keynote Speaker at the International Conference on Water, Environment, Energy and Society, paper How to Motivate Machines to Learn and Help Humans in Making Water Decisions? New Delhi, India, Jan. 12-16, 2009.

 

Ø      The Keynote Speaker at the UNESCO strategic workshop, Integrated Modelling Approaches to Support Water Resource Decision Making: Crossing the Chasm, Paris, France, April 20-22, 2009.

 

 

RESEARCH GRANTS AND CONTRACTS FUNDED (TOTAL $3,456,226)

 

Year

Sponsor

Topic

Amount

1984

Valid Logic Inc.           

Equipment Grant for VLSI lab.

$167,010

1986

National Bureau of Standards         

Development of Testing Strategies for Very Large Analog Circuits

$ 21,571

1987

 Texas Instruments 

Software Grant for IBM PC Lab. 22 copies of PC Scheme

$  2,200

1987

DARPA/NSF   

Fabrication of Prototype VLSI Circuits  

$  6,400

1987

National Bureau of Standards

Development of Testing Strategies for Large Nonlinear Circuits

$ 54,940

1988

National Bureau of Standards

Time Domain and Frequency Domain Testing of Large Nonlinear Circuits           

$120,375

1989

 National Institute of Standards and Technology

Testing Strategies for Large Mixed Mode Circuits

$ 50,069

1989

Microsim Corporation               

Software for Sun Worksations 7 copies of PSpice Deluxe A/D

$ 66,950

1989

Stocker Fund                      

Sun Workstations for VLSI, Microwave and Image processing Lab

$46,172

1990

Valid Logic Inc.                                               

Software for VLSI design on Sun workstations

$310,000

1991

Magnetek Corp.           

Testability Design of PC Power Supplies           

$ 10,000

1992

National Institute of Standards and Technology

A Feasibility Study for On-Line Error Detection in Analog Systems

$ 19,965

1994

National Institute of Standards and Technology

Modeling and Verification Procedures for Self-Calibrating Systems

$ 23,697

1994

Mentor Graphics

Design and Simulation Software

 $1,800,000

1996

View Logic      

WorkWiew Office Software             

$30,000

1997

State Committee for Scientific Research

1 year Grant Supporting Cooperation Between WUT and Ohio University

$4,500

1997

AFOSR

Feature Selection for Automatic Target Recognition

$27,535

1997

Sarnoff Research

Reengineering of Intel 8031 Microprocessor

$32,197

1998

Xilinx

Software and hardware for FPGA

$25,922

1998

University of Cincinnati

Application of scalability and testability in mechatronic design environment

$16,085

1998

National Institute of Standards and Technology

Testing Strategies for Mixed Signal Embedded Systems

$44,950

1988

Sverdrup Technology Inc.

Evolutionary Feature Extraction for SAR Air to Ground Moving Target Recognition – Statistical Approach

$25,000

1998

AFOSR

Feature Extraction for Air to Ground HRR Radar ATR Based on Mutual Information and Statistical Techniques

$144,180

1999

AFOSR

 

Feature Selection for Automatic Target Recognition

$27,535

 

1999

Sarnoff Research

Pass Transistor Library Development

$9,661

1999

National Institute of Standards and Technology

Testing Strategies for Mixed Signal Embedded Systems                                                                                                         

$9,636

2000

Avionics Engineering Center

GPS research                                                                                     

$75,000

2001

Avionics Engineering Center

GPS signal acquisition and processing                                                                                        

 

$45,000

2001

Xilinx

10 Spartan Boards,

core generator software

$15,000

2001

Sarnoff Research

Design of 14bit DAC in 0.13um CMSO

$96,000

2002

Magnolia Broadband

Design of 5.5 GHz CMOS Fully Integrated Tunable VCO

$26,818

2002

Avionics Engineering Center

GPS signal acquisition and processing                                                                   

 

$30,000

2002

Xilinx

480 XCV1000 chips

$244,500

2002

Xilinx

10 Spartan Boards for VHDL lab                                                                            

$8,000

2002

Magnolia Broadband

PLL Design for CDMA 2000 in SiGe

$14,529

2003

Sensors Directorate, Air Force Research Laboratory

Two Sun-Spark workstations and dedicated FPGA based hardware

$50,000

2003

Magnolia Brodaband

Design of Integrated VCO for CDMA2000                                                           

$7,250

2003

Xilinx

XCV100-5BG560C for SOLAR research                                                               

$3,070

2003

Avionics Engineering Center

GPS signal acquisition and processing                                                                  

 

$25,000

2004

Xilinx

System generator and PCI development kit                                                    

$28,581

2005

AFORS

Collaborative Sensing and Threat Awareness in Urban Operation

$22,000

2005

EVIS LLC

Equipment grant to design a rowing control system      

  $5,000

2006

AFOSR

Challenges and Promises of Embodied Intelligence

$18,000

2006

Anteon Corporation, a General Dynamics Company

Neural Network Self-Organization and

Extracting Video Game Data for Machine Learning

$16,000

2007 Anteon Corporation, a General Dynamics Co. Extracting Video Game Data for Machine Learning

$8,000

Total funds received

$3,826,298

 

 

COURSES TAUGHT

 

Graduate:

Ø      EE616              Computer Aided Analysis of Electronic Circuits

Ø      EE617                          Design for Testability

Ø      EE690              VLSI Design of Neural Networks

Ø      EE690              Design of Intelligent Systems

Ø      EE716              Active Network Theory

Ø      EE819              Graph Theory

 

Undergraduate:

Ø      EE415              VLSI Design

Ø      EE414              VHDL Design

Ø      EE495              ECE Capstone Design

Ø      EE222              Introduction to Digital Circuits

Ø      EE312              Linear Systems and Networks

Ø      EE343              Electronics

Ø      EE210              Circuit Theory

Ø      EE411              Passive Filter Synthesis

Ø      EE323              Analytical Foundations of Electrical Engineering

 

Laboratories:

Ø      EE401              VLSI design laboratory

Ø      EE402              VHDL design laboratory

 

THESES AND DISSERTATIONS COMPLETED    

 

Master of Science

 

No

Name

Date

Thesis Title

1

Jerzy Romaniuk

1979

Optimization of Railway Traction Using Graph Methods

2

Edward Sliwa

1979

Computer Programs for Analysis of Large Unistor Graphs

3

Zbigniew Calka

1980

Topological Synthesis of Active Networks Using Unistor Graphs

4

Jerzy Kotkowski

1981

Topological Analysis of Switched Capacitor Circuits Using Signal‑Flow Graph Representation

5

Eric M. Schwarz

1984

Parallel Processing and VLSI Design: Solving Large‑Scale Linear Systems

6

Hong Dai

1985

Network Approach to Impedance Computerized Tomography

7

Venkata S.R. Dandu

1985

Parallel Processing and VLSI Design: A High Speed Efficient Multiplier

8

Fadi M. Kaake

1986

A VLSI‑nMOS Hardware Implementation of an IIR Bandpass Orthogonal Digital Filter

9

Venkatram R. Chintala

1986

Digital Image Data Representation

10

Soheil Davati

1986

VLSI Implementation of Recursive Digital Notch Filter

11

I‑Sheng Yang

1986

An Impedance Scanner (project in non thesis option)

12

George M. Mourad

1986

Built‑in Testable Structure for VLSI Circuits (project in non thesis option)

13

Kang‑Chung Chiang

1986

Scan Path Design of PLA to Improve its testability in VLSI Realization

14

Luis A. Montalvo

1986

VLSI Implementation of Control Section of Overlapped 3‑bit Scanning 64‑bit Multiplier

15

Hoon‑Kyeu Lee

1986

Automatic Test Pattern Generation in the Logic Gate Level Circuits and MOS Transistor Circuits

16

Samboon Taesopapong

1986

A VLSI‑nMOS Hardware Implementation of a High Speed Parallel Adder

17

Chung-nan Lyu

1988

Pipelined Floating Point Divider with Built-in Testing Circuits

18

Elie N. Talej     

1988

A VLSI Design of a Finite Impulse Response Low-Pass Digital Filter

19

Chengbu Kim

1988

One-Dimensional Compaction Strategy for VLSI Symbolic Layout System

20

Chao-Wu Chen

1988

Design and nMOS Implementation of Parallel Pipelined Multiplier

21

Hsein-Jung Mao

1988

VLSI Design and Implementation of a Parallel Sorter

22

Mohammad Eshghi

1988

Highly Parallel Transversal Adaptive Filters

23

Chin Aik Le

1988

An 8-bit Inner Product Multiplier by Parallel Pipeline Algorithm

24

Chung Chih-Ping

1989

Setting CMOS Environment for VLSI Design

25

Xiaoming Wu

1991

Approximation Using Linear Fitting Neural Network: Polynomial Approach and Gaussian Approach

26

Youping Chen

1991

Neural Network Approximation for Linear Fitting Method

27

Sin Wo Kuan

1992

VLSI Implementation of Neural Network for Character Recognition Application

28

Chang-Chyh Hsiao

1992

Design of VLSI CMOS Systems Using MAGIC

29

Nasser Ansari

1992

Handwritten Character Recognition by Using Neural Network Based Methods

30

Ying-Wei Jan

1994

Segmentation and Clustering in Neural Networks for Image Recognition

31

Senthilkumar Manickavasagam

1996

A+B Arithmetic - Theory and Implementation

32

Zheng Chen

1997

VLSI Implementation of a High-Speed Delta-Sigma Analog to Digital Converter

33

Abdulqadi Al_Aqeeli

1998

FPGA Realization of Haar Wavelet for Pattern Recognition

34

Raja D.V. Bhupatiraju

1998

A Comparative Study of High Speed Adders

35

Chirag Patel

1999

A Time-to-Voltage Converter

36

Fengjing Qiu

1999

Analog VLSI Design of Two‑Phase and Multi‑Phase Voltage Doublers with  Frequency Regulation

37

Aman Sareen

1999

Reconfigurable Design for Pattern Recognition Using Field Programmable Gate Arrays

38

Phillip Southard

2000

Design Methodology for Modeling a Microcontroller

39

Sanjeev  Gunavardena

2000

Feasibility Study for the Implementation of Global Positioning System Block Processing Techniques in Field Programmable Gate Arrays

40

Zhu Zhen

2002

Averaging Correlation for Weak Signal Global Positioning System Signal Processing

41

Tsun Ho Liu

2002

Future Hardware Realization of Self-Organizing Learning Array and its Software Simulation

42

Guo, Yongtao

2004

PicoBlaze Based Self Organizing Learning Array and its Experimental Setting

43

Feng, Wang 

2004

Energy Efficient Digital Baseband Modulator for Cable Terminal Systems Targeted on Field Programmable Gate Array

44

Li, (Yue) Lily

2006

Active Vision through Invariant Representations and Saccade Movements

45 James Graham 2007 Efficient Generation of Reducts and Discerns for Classification
46 Amit Borundiya 2008 Implementation of Hopfield Neural Network Using Double Gate MOSFET
47 Yiming Huang 2009 Phoneme Recognition Using Neural Network and Sequence Learning Model

 

Philosophy Doctor

 

No

Name

Date

Dissertation Title

1

Hong Dai

1989

Development of Decomposition Approach for Testing Large Analog Circuits 

2

Mohamed Abd El-Gamal

1990

Fault Location and Parameter Identification in Analog Circuits

3

Chiung-Hsing Chen

1994

Inner-Product Based Signal Processing: Algorithms and VLSI Implementation

4

Xuefeng Fang

1994

Small Area, Low Power, Mixed-Mode Circuits for Hybrid Neural Network Applications

5

Sinkuo Chai

1995

Multiclassifier Neural Networks for Handwritten Character Recognition

6

Zhi-Hong Liu

1998

Mixed-Signal Testing of Integrated Analog Circuits and Modules

7

Ying-Wei Jan

1998

A Switched-Capacitor Analysis of MOS Circuit Simulator:  SAMOC

8

Dale Nelson

2001

High Range Resolution Radar Target Classification: A Rough Set Approach

9

Ahmad Alsolaim

2002

Dynamically Reconfigurable Architecture for Third Generation Mobile Systems

10

Abdulqadir Alaqeeli

2002

Global Positioning System Signal Acquisition and Tracking Using Field Programmable Gate Arrays

11

Pang, Jing

2003

Direct Global Positioning System P-Code Acquisition Field Programmable Gate Array Prototyping

12

Liu, Dong

2003

Analog and Mixed Signal Test and Fault Diagnosis.

13

Ding, Mingwei

2005

High Level Design Methodology for Reconfigurable Systems

14

He, Haibo

2006

Dynamically Self-Reconfiguarable Systems for Machine Intelligence

15

Zhen, Zhu

2006

Characterization of Global Positioning System Earth Surface Multipath and Cross Correlation for Aircraft Precision Approach Operations using Software Radio Technology

16 Yinyin Liu 2009 Hierarchical Self-organizing Learning Systems for Embodied Intelligence

 

 

PROFESSIONAL ACTIVITIES

 

   Professional memberships

Ø      Senior Member of the Institute of Electrical and Electronics Engineers

-          Circuits and Systems Society

-          Computer Society

Ø      Member of the American Society of Naval Engineers

Ø      Member of the Association for Computing Machinery

Ø      Member of American Society for Engineering Education

Ø      Member of the Association of Professional Engineers of Ontario

 

   Referee of journals

IEEE Transactions on Circuits and Systems, IEEE Transactions on Computers, IEEE Transactions on Neural Networks, IEEE Transactions on Instrumentation and Measurement, IEEE Transactions on Computer Aided Design, IEEE Transactions on Design and Test of Computers, IEEE Transactions on Electromagnetic Compatibility, IEE Proceedings-G Circuits, Devices and Systems, International Journal of Circuit Theory and Applications, International Journal Computers and Mathematics with Applications, Journal of Electronic Testing, Journal of Neurocomputing, Kluwer Academic Publishers, Elsevier Engineering Applications of Artificial Intelligence, Bulletin of International Rough Set Society, Archiwum Elektrotechniki.

 

   Referee of conferences

International Conference on Artificial Intelligence and Applications, International Conference Artificial Neural Networks, International Conference on Signals and Electronic Systems, International Multiconference on Computer Science and Information Technology, ACM/IEEE Design Automation Conference, Artificial Neural Networks in Engineering, Design Automation and Test in Europe, European Conference on Circuit Theory and Design, IEEE International Conference on Computer Design: VLSI in Computers, IEEE International Symposium on Circuits and Systems, IEEE VLSI Test Symposium, International Conference on VLSI Design, International Conference on Parallel Processing, International Test Conference, International Workshop on Intelligent Signal Processing and Communication Systems, Midwest Symposium on Circuits and Systems, OAI Workshop on Neural Networks.

 

COMMITTEES AND SERVICES

 

Professional Service

Ø      International Program Committee Member, IASTED International Conference on Artificial Intelligence and Applications, Innsbruck, Austria, Feb. 12-14, 2007.

Ø      Scientific Committee Member, The International Conference on Signals and Electronic Systems, ICSES'06, Lodz, Poland, Sep. 17-20, 2006.

Ø      Technical Committee Member, First International Multiconference on Computer Science and Information Technology, Wisla, Poland, November 6-10, 2006.

Ø      Session Chair, International Conference Artificial Neural Networks, Warsaw, Poland, Sep. 11-15, 2005.

Ø      Founding Member of the Institute for Applications of the Mathematical Sciences at Ohio University, 2004.

Ø      Technical Committee Member, International Conference Design Automation and Test in Europe, Paris, France, Feb. 16-20, 2004.

Ø      Technical Committee Member, International Conference Design Automation and Test in Europe, Paris, France, March 2002.

Ø      Member of NSF Information Technology Research (ITR) panel, 2001.

Ø      Board of Examiners, Indian Institute of Technology, Delhi, India, 1999.

Ø      Technical Committee Member, Workshop on the Software Embedded System Test, Gaithersburg, MD, Nov. 7-11, 1999.

Ø      Planning Committee Member, Edison Electronic Technology Center in Ohio, 1998.

Ø      IEEE Working Group for P1149.4 Mixed-Signal Test Bus Standards 1992-1997.

Ø      Technical Program Committee Member, OAI Neural Networks Symposium 1995.

Ø      Technical Program Chairman, IEEE Southeastern Symposium on System Theory 1994.

Ø      Technical Program Committee Member, International Workshop on Intelligent Signal Proc. and Communication Systems 1992.

Ø      Technical Committee Member, European Conference on Circuit Theory and Design, Warsaw, Poland 1980.

 

University and College Committees

Ø      Institute of Electronic Fundamentals, Director's Advisory Committee (1978‑80).

Ø      Stocker Fund Planning and Advisory Committee (1991-95, 2005-).

Ø      Ohio University Library Committee (1996-98)

Ø      Graduate Council (1985‑88).

Ø      Chairman of the Fellowship Board (1998).

Ø      Policies and Regulations (1999).

Ø      Graduate Research Council (2004-2006).

 

Departmental Committees

Ø    Chairman of VLSI Committee (1983‑  ).

Ø    Chairman of Research Committee (1991-99).

Ø    Chairman of ECE Library Committee (1991-97).

Ø    Graduate Committee Chairman in Networks and Electronics (1983‑ ).

Ø    Computer Committee (1983/84).

Ø   Curriculum Committee (1986/87).

Ø   Core Courses Committee in Circuits and Analytics (1994-1996).

Ø    Chairman of the ECE Seminar Series (1985‑87, 1996-97).

Ø   Www Committee (1998-2002).

Ø   Annual Review and Raise Allocation Advisory (2000-2003).

Ø   Undergraduate Course Committees: EE Senior Design Committee,         Advanced EE 3**,4** (2000-)

Ø    Promotion and Tenure Committee (1994-1997, 2003-2006)

 

HONORS AND AWARDS

Ø      Nominated for the grade of IEEE Fellow.

Ø      Listed in Who's Who in Engineering Education

Ø      Award of the Ministry of Science and Higher Education for outstanding research

Ø      Outstanding teacher award Technical University of Warsaw

Ø      Honor Society - Eta Kappa Nu

Ø      Nominated to the Outstanding Graduate Faculty Award at Ohio University twice.

Ø      The Keynote Speaker at the VII Riunione Annuale Dei Ricercatori, Trani, Italy.

Ø      The Keynote Speaker at the System on a chip and Reconfigurable Computing Workshop, Riyadh, Saudi Arabia, 2000.

Ø      Best paper award in Mathematical Methods and Optimization in Problem Solving System - 4th World Multiconf. on Systemic, Cybernetics and Informatics, Orlando FL, July, 2000.

Ø      Certificate for outstanding inventive contributions to Ohio University Intellectual Property 1999-2000.

Ø      Best session paper at the SPIE 15th Annual Int. Symp. on Aerospace/Defense Sensing Simulation and Controls, Orlando FL, April 2001.

Ø      The Keynote Speaker at the The International Conference on Signals and Electronic Systems, ICSES'06, Lodz, Poland, Sep. 17-20, 2006.

Ø      The Keynote Speaker at the International Conference on Artificial Intelligence, Siedlce, Poland, Sept. 21-22, 2006.

Ø      Computational Intelligence Society Outstanding 2005 Paper Award Nomination (J. A. Starzyk, Z. Zhu and T.-H. Liu) IEEE Transaction on Neural Networks.  Paper title:  "Self-Organizing Learning Array".

Ø      The best research paper award in the College of Engineering and Technology at Ohio University for 2007 (J. A. Starzyk, and H. He) “Anticipation-Based Temporal Sequences Learning in Hierarchical Structure”, IEEE Trans. on Neural Networks.

Ø      The Keynote Speaker at the International Conference on Water, Environment, Energy and Society, New Delhi, India, Jan. 12-16, 2009.

Ø      The Keynote Speaker at the UNESCO strategic workshop, Integrated Modelling Approaches to Support Water Resource Decision Making: Crossing the Chasm, Paris, France, April 20-22, 2009.