Former PhD Students, Dissertation Title, and Whereabouts
  1. Basawaraj PhD 2019 Implementation of Memory for Cognitive Agents Using Biologically Plausible Associative Pulsing Neurons, Research Engineer, Ohio University, Athens, Ohio.  
  2. Graham, James PhD 2016 Development of Functional Requirements for Cognitive Motivated Machines, Senior Broadcast Engineer, Wright State Foundation, 3640 Colonel Glenn Hwy, Dayton, OH 45435-0001,  
  3. Nguyen, Vu-Anh PhD 2012 Neural Network Structure for Spatio-Temporal Long-Term Memory: Theory and Applications.  
  4. Raif, Pawel PhD 2011 Simulation Research and Development of the Learning Method based on Goal Creation.  
  5. Yinyin Liu PhD 2009 Hierarchical Self-organizing Learning Systems for Embodied Intelligence,  
  6. He, Haibo PhD 2006 Dynamically Self-Reconfiguarable Systems for Machine Intelligence, Assistant Professor, Department of Electrical, Computer, and Biomedical Engineering, University of Rhode Isleand , RI. http://www.ele.uri.edu/
  7. Zhen, Zhu PhD 2006 Characterization of Global Positioning System Earth Surface Multipath and Cross Correlation for Aircraft Precision Approach Operations using Software Radio Technology, Research Engineer, Ohio University, Athens, OH.
  8. Ding, Mingwei PhD 2005 High Level Design Methodology for Reconfigurable Systems, Field Application Engineer, Intel, China.
  9. Liu, Dong PhD 2003 Analog and Mixed Signal Test and Fault Diagnosis, Sr. Analog Design Engineer, Logging Services, ESG, Halliburton, Houston, TX, http://www.halliburton.com/.
  10. Pang, Jing PhD 2003Direct Global Positioning System P-Code Acquisition Field Programmable Gate Array Prototyping, Associate Professor, Electrical and Electronic Engineering, California State University, Sacramento, CA.
  11. Al_Aqeeli, Abdulqadi PhD 2002 Global Positioning System Signal Acquisition and Tracking Using Field Programmable Gate Arrays, Assistant Professor, Telecommunication Department at the College of Telecommunication and Information in Riyadh, Saudi Arabia
  12. Alsolaim, Ahmad PhD 2002 Dynamically Reconfigurable Architecture for Third Generation Mobile Systems, Chairman of the EE Tech Department at the Riyadh Tech College.
  13. Nelson, Dale E.  PhD 2001 High Range Resolution Radar Target Classification:  A Rough Set Approach, Chief   Target Recognition Branch, Air Force Research Laboratory
  14. Liu, Zhi Hong PhD 1998 Mixed-Signal Testing of Integrated Analog Circuits and Modules, Employed by Ford Electronics, Detroit, Michigan.
  15. Jan, Ying-Wei PhD 1998 A Switched-Capacitor Analysis of MOS Circuit Simulator:  SAMOC, Assistant Professor, Dept. of Electronic Engineering of I-Shou University, Kaohsiung, Taiwan ROC.
  16. Sinkuo Chai PhD 1995 Multiclassifier Neural Networks for Handwritten Character Recognition, Associate Professor, Tai Chung College, Taiwan ROC.
  17. Chiung-Hsing Chen PhD 1994 Inner-Product Based Signal Processing: Algorithms and VLSI Implementation, Associate Professor, Chairman, Dept. of Electronic and Communication Engineering, National Kaohsiung Inst. of Marine Technology, Taiwan ROC.
  18. Xuefeng Fang PhD 1994 Small Area, Low Power, Mixed-Mode Circuits for Hybrid Neural Network Applications, Employed by Integrated Device Technology Inc., Atlanta, Georgia.
  19. Mohamed Abd El-Gamal PhD 1990 Fault Location and Parameter Identification in Analog Circuits, Associate Professor, Engineering Mathematics and Physics Department, Cairo University, Egypt.
  20. Hong Dai PhD 1989 Development of Decomposition Approach for Testing Large Analog Circuits, Test Engineer, AMCC, San Diego, California.
Former MS Students and Thesis Title
  1. Yiming, Huang  MS 2009 Phoneme Recognition Using Neural Network and Sequence Learning Model.
  2. Borundiya, Amit MS 2008 Implementation of Hopfield Neural Network Using Double Gate MOSFET
  3. James T. Graham MS 2007 Efficient Generation of Reducts and Discerns for Classification
  4. Li, (Yue) Lily MS 2006 Active Vision through Invariant Representations and Saccade Movements
  5. Guo, Yongtao MS 2004 PicoBlaze Based Self Organizing Learning Array and its Experimental Setting

  6. Feng, Wang  MS 2004 Energy Efficient Digital Baseband Modulator for Cable Terminal Systems Targeted on Field Programmable Gate Array , received PhD from Penn State University in 2008. Works as a research engineer at Qualcomm, CA, San Diego.  

  7. Liu, Tsun-Ho MS 2002 Future Hardware Realization of Self-Organizing Learning Array and its Software Simulation

  8. Zhu, Zhen MS 2002 Averaging Correlation for Weak Signal Global Positioning System Signal Processing received PhD from Ohio University in Characterization of Global Positioning System Earth Surface Multipath and Cross Correlation , 2006. Works as research engineer at Avionics Engineering Center, Ohio University.
  9. Gunavardena, Sanjeev MS 2000 Feasibility Study for the Implementation of Global Positioning System Block Processing Techniques in Field Programmable Gate Arrays currently a PhD student at Ohio University.
  10. Southard, Phillip MS 2000 Design Methodology for Modeling a Microcontroller
  11. Patel, Chirag MS 1999 A Time-to-Voltage Converter
  12. Qiu, Fengjing MS 1999 Analog VLSI Design of Two-Phase and Multi-Phase Voltage Doublers with Frequency Regulation
  13. Sareen, Aman MS 1999 Reconfigurable Design for Pattern Recognition Using Field Programmable Gate Arrays
  14. Al_Aqeeli, Abdulqadi MS 1998 FPGA Realization of Haar Wavelett for Pattern Recognition received PhD from Ohio University in Global Positioning System Signal Acquisition and Tracking using FPGA, 2002.Works in Telecommunication Department at the College of Telecommunication and Information in Riyadh, Saudi Arabia.
  15. Bhupatiraju, Raja MS 1998 A Comparative Study of High Speed Adders
  16. Chen, Zheng MS 1997 VLSI Implementation of a High-Speed Delta-Sigma Analog to Digital Converter
  17. Senthilkumar Manickavasagam MS 1996 A+B Arithmetic - Theory and Implementation
  18. Ying-Wei Jan MS 1994 Segmentation and Clustering in Neural Networks for Image Recognition
  19. Sin Wo Kuan MS 1992 VLSI Implementation of Neural Network for Character Recognition Application
  20. Chang-Chyh Hsiao MS 1992 Design of VLSI CMOS Systems Using MAGIC
  21. Nasser Ansari MS 1992 Handwritten Character Recognition by Using Neural Network Based Methods
  22. Xiaoming Wu MS 1991 Approximation Using Linear Fitting Neural Network: Polynomial Approach and Gaussian Approach
  23. Youping Chen MS 1991 Neural Network Approximation for Linear Fitting Method
  24. Chung Chih-Ping MS 1989 Setting CMOS Environment for VLSI Design
  25. Chung-nan Lyu MS 1988 Pipelined Floating Point Divider with Built-in Testing Circuits
  26. Elie N. Talej MS 1988 A VLSI Design of a Finite Impulse Response Low-Pass Digital Filter
  27. Chengbu Kim MS 1988 One-Dimensional Compaction Strategy for VLSI Symbolic Layout System
  28. Chao-Wu Chen MS 1988 Design and nMOS Implementation of Parallel Pipelined Multiplier
  29. Hsein-Jung Mao MS 1988 VLSI Design and Implementation of a Parallel Sorter
  30. Mohammad Eshghi MS 1988 Highly Parallel Transversal Adaptive Filters, received PhD from Ohio State University, 1994.
  31. Chin Aik Le MS 1988 An 8-bit Inner Product Multiplier by Parallel Pipeline Algorithm,
  32. Fadi M. Kaake MS 1986 A VLSI-nMOS Hardware Implementation of an IIR Bandpass Orthogonal Digital Filter
  33. Venkatram R. Chintala MS 1986 Digital Image Data Representation
  34. Soheil Davati MS 1986 VLSI Implementation of Recursive Digital Notch Filter
  35. I-Sheng Yang MS 1986 An Impedance Scanner (project in nonthesis option)
  36. George M. Mourad MS 1986 Built-in Testable Structure for VLSI Circuits (project in nonthesis option)
  37. Kang-Chung Chiang MS 1986 Scan Path Design of PLA to Improve its testability in VLSI Realization
  38. Luis A. Montalvo MS 1986 VLSI Implementation of Control Section of Overlapped 3-bit Scanning 64-bit Multiplier
  39. Hoon-Kyeu Lee MS 1986 Automatic Test Pattern Generation in the Logic Gate Level Circuits and MOS Transistor Circuits, received PhD from Chungnam Natioanl University in Microwave and Optical Electronics, August 2000, President TRISMED CO., LTD.
  40. Samboon Taesopapong MS 1986 A VLSI-nMOS Hardware Implementation of a High Speed Parallel Adder
  41. Hong Dai MS 1985 Network Approach to Impedance Computerized Tomography, received PhD from Ohio University in Testing Large Analog Circuits, 1989; works as Test Engineer, AMCC, San Diego, California.
  42. D.V.S. Raju (Venkata S.R. Dandu) MS 1985 Parallel Processing and VLSI Design: A High Speed Efficient Multiplier, Chairman and Managing Director VisualSoft Technologies.
  43. Eric M. Schwarz MS 1984 Parallel Processing and VLSI Design: Solving Large-Scale Linear Systems, received PhD from Stanford University in Computer Arithmetic, August 1990, works for IBM Corp., Decimal Floating-Point Hardware.

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