Recent Papers

J. A. Starzyk, “Topological Analysis and Diagnosis of Analog Circuits”, Wydawnictwa Politechniki Slaskiej, 2008, 140 pp.

H. F. A. Hamed, S. Kaya, J. A. Starzyk, “Use of nano-scale double-gate MOSFETs in low-power tunable current mode analog circuits” Analog Integrated Circuits and Signal Processing, Feb., 2008.

Z. Zhu, F. van Graas and J. A. Starzyk, “GPS signal acquisition using the repeatability of successive code phase measurements” GPS Solutions, Springer, May 2007.

S. Kaya, H. F. A. Hamed and J. A. Starzyk, “Low-Power Tunable Analog Circuit Blocks Based on Nanoscale Double-Gate MOSFETs,” IEEE Trans. Circuits Syst. II, vol. 54, no. 7, July 2007, pp. 571-575.

J. A. Starzyk, Dong Liu, Zhi-Hong Liu, D. Nelson, and J. Rutkowski, “Entropy-based optimum test points selection for analog fault dictionary techniques,” IEEE Transactions on Instrumentation and Measurement, vol. 53, no. 3, June 2004, pp. 754-761.

J. A. Starzyk, R. P. Mohn, and L. Jing, L., "A Cost-Effective Approach to the Design and Layout of a 14-b Current-Steering DAC Macrocell", IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, Vol. 51 ,  no. 1 , Jan. 2004, pp. 196 - 200.

D. Liu and J. A. Starzyk, " A generalized fault diagnosis in dynamic analog circuits" Int. Journal of Circuit Theory and Applications, vol. 30, 2002, pp. 487-510.

J. Becker, A. Alsolaim, M. Glesner, and J. Starzyk, “A Parallel Dynamically Reconfigurable Architecture for Flexible Aplication-Tailored Hardware/Software Systems in Future Mobile Communication”, The Journal of Supercomputing, Erratum Vol. 23, 132, 2002,  19(1): 105-127 (2001).

J. Pang and J. A. Starzyk, "Fault Diagnosis in Mixed-Signal Low Testability System" An Int. Journal of Analog Integrated Circuits and Signal Processing, vol. 28, no.2, August 2001, pp. 159-170.

J. A. Starzyk and Y.-W. Jan, and F. Qiu, "A DC-DC Charge Pump Based on Voltage Doublers", IEEE Trans. Circuits and Systems, Part I, vol. 48, no. 3, March 2001, pp. 350-359.

J. Pang, J. A. Starzyk, "P-code Generator FPGA Design for Direct GPS P(Y)-Code Acquisition", 12th International Conference on Field Programmable Logic and Applications (FPLA), 2002.

M. Ding, A. Alsolaim, and J. Starzyk, "Designing and Mapping of a Turbo Decoder for 3G Mobile Systems Using Dynamically Reconfigurable Architecture " Engineering of Reconfigurable Systems and Algorithms, ERSA'02, The Int. Multi Conference in Computer Science, June 24-27, Las Vegas, Nevada, 2002.

J. A. Starzyk Y. Guo, "A Self Organized Classifier Based on Maximum Information Index and its Develpoment Using VHDL", 2002 IEEE Int. Symposium on Intelligent Signal Processing and Communication Systems, 21-24 November 2002, Kaohsiung, Taiwan, R.O.C. 2002.

J. A. Starzyk and L. Jing, "Analog Circuits for Self Organizing Neural Networks Based on Mutual Information" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001).

A. Alaqeeli and J. A. Starzyk, "Hardware Implementation of Fast Convolution for GPS Signal Acquisition Using FPGA" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001).

A.Alsolaim and J. A. Starzyk, "Dynamically Reconfigurable Solution in the Digital Baseband Processing for Future Mobile Radio Devices" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001).

J. A. Starzyk and Y. Guo, "An Entropy-based Learning Hardware Organization Using FPGA" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001).

J. A. Starzyk and Y. Guo, "Reconfigurable Self-Organizing NN Design Using Virtex FPGA", Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (Las Vegas, NV, June 2001).

A. Alsolaim, J. Becker, M. Glesner, and J. Starzyk, "A Dynamically Reconfigurable System-on-a chip Architecture for Future Mobile Digital Signal Processing", The European Signal Processing Conference EUSIPCO, (Sept. 5 - 8, 2000, Tampere, Finland).

J. Becker, M. Glesner, A. Alsolaim, J. Starzyk, "Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures", the 2000 Int. Conf. on Parallel and Distributed Processing Techniques and Apllications, (Las Vegas, NV, June 2000).

A. Alsolaim, J. Becker, M. Glesner, J. Starzyk. "Dynamically Reconfigurable Array Architecture for Future Mobile Digital Baseband Processing." 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), April 16-19, 2000, Napa Valley, California.

J. Starzyk and J. Pang, "Evolvable Binary Artificial Neural Network for Data Classification", the 2000 Int. Conf. on Parallel and Distributed Processing Techniques and Apllications, (Las Vegas, NV, June 2000).

F. Qiu, J. A. Starzyk and Y.-W. Jan, "Analog VLSI Design of Multi-phase Voltage Doublers with Frequency Regulation", the 1999 Southwest Symposium on Mixed-Signal Design, (Tucson, AZ, April, 1999).

J. A. Starzyk and Y.-W. Jan," A Simulation Program Emphasized on DC Analysis of VLSI Circuits: SAMOC", the 1999 Southwest Symposium on Mixed-Signal Design, (Tucson, AZ, April, 1999).

Papers before 1997

J. A. Starzyk and X. Fang, "A CMOS Current Mode Winner-Take-All Circuit with both Excitatory and Inhibitory Feedback", Electronics Letters, 1993.

J. A. Starzyk, "Hierarchical Analysis of High Frequency Interconnect Networks", IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol.13, no.5, 1994, pp. 658-664.

J. A. Starzyk, "Decomposition Approach to a VLSI Symbolic Layout with Mixed Constraints", Proc. IEEE Int. Symp. Circuits and Systems (Montreal, 1984). pp. 457-460.

J. A. Starzyk and V.S.R. Dandu, "Overlapped Multi-Bit Scanning Multiplier", Proc. IE Computer Design: VLSI in Computers (Port Chester, NY, 1985).

J. A. Starzyk and M. Eshghi, "Highly Parallel Adaptive Filter," Proc. IEEE Int. Symp. Circuits and Systems (Portland, OR, 1989).

J. A. Starzyk and C. H. Chen, "A One Dimensional Processor Array for LU Decomposition", Proc. IEEE Int. Workshop on Intelligent Signal Processing and Communication Syst. (Taipei, Taiwan, ROC, 1992).

X. Fang and J. Starzyk, "A novel winner-take-all circuit", the World Conf. on Neural Networks, (Portland, OR, 1993).

J. A. Starzyk and X. Fang, "System level design of a complex neural network for target recognition", IEEE Int. Conf. on Neural Network Applications to Signal Processing, (Singapore, 1993).

J. A. Starzyk and C.-H. Chen, "A VLSI Inner Product Processor with Built-in Self Test for Real Time DSP Applications", Int. Conf. on Signal Proc. Applications and Technology, (Santa Clara, CA, 1993).

X. Fang and J. A. Starzyk, "VLSI design of neural network based image processor", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

J. A. Starzyk and Y-W. Jan, "Algorithm and architecture for feature extraction in image processing", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

J. A. Starzyk and C-H. Chen, "A VLSI inner-product processor for real-time DSP applications", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

J. A. Starzyk and M. Senthil Kumar, "Partial arithmetic - algorithms and architecture", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

J. A. Starzyk and Ying-Wei Jan, "Low Power Voltage Based Winner Takes All Circuit for Analog Neural Networks", OAI Neural Network Symposium, (Athens, OH, 1995).

J. A. Starzyk and Ying-Wei Jan, "A Voltage Based Winner Takes All Circuit for Analog Neural Networks", Proc. Midwest Symp. on Circuits and Systems (Ames, Iowa, 1996).