Conference papers before year 2000

1. F. Qiu, J. A. Starzyk and Y.-W. Jan, "Analog VLSI Design of Multi-phase Voltage Doublers with Frequency Regulation", the 1999 Southwest Symposium on Mixed-Signal Design, (Tucson, AZ, April, 1999).

2. J. A. Starzyk and Y.-W. Jan," A Simulation Program Emphasized on DC Analysis of VLSI Circuits: SAMOC", the 1999 Southwest Symposium on Mixed-Signal Design, (Tucson, AZ, April, 1999).

3. G. N. Stenbakken, D. Liu, J. A. Starzyk and B. C. Waltrip, "A new method to compensate quantized time-base nonlinearity of sampling instruments," Workshop on Software Embedded Systems Testing (WSEST), National Institute of Standards and Technology, Gaithersburg, MD, Nov. 1999.

4. V. Brygilevicz, J. Wojciechowski, and J. A. Starzyk, "Testing of Analog Dynamic Systems Based on Integral Sensisitivity", Proc. ECCTD, (Stresa, Italy, Aug. 1999).

5. J.A. Starzyk, J. Pang, G. Fedi, R. Giomi, S. Manetti, "A Software Program for Ambiguity Group Determination in Low Testability Analog Circuits", Proc. ECCTD, (Stresa, Italy, Aug. 1999).

6. R. Morawski, B. Manhire, and J. Starzyk, "Engineering Education in Poland", ASEE Conf., Seattle, June, 1998.

7. J. A. Starzyk, D. E. Nelson, and K. Sturtz, "Reduct Generation in Information Systems", The Sixth Int. Workshop on Rough Sets, Data Mining and Granular Computing, at JCIS'98, (Research Triangle Park, NC), Oct. 1998.

8. D. E. Nelson and J. A. Starzyk, "Advanced Feature Selection Methodology for Automatic Target Recognition", Proc. Southeastern Symposium on System Theory, (Coolville, TN, 1997).

9. Z-H. Liu and J. A. Starzyk, "Mixed Signal Testing of Analog Components on Printed Circuit Boards", Proc. Midwest Symp. on Circuits and Systems (Sacramento, CA, 1997).

10. J. A. Starzyk and J. Zou, "Direct Symbolic Analysis of Analog Networks", Proc. Midwest Symp. on Circuits and Systems (Ames, Iowa, 1996).

11. J. A. Starzyk and Ying-Wei Jan, "A Voltage Based Winner Takes All Circuit for Analog Neural Networks", Proc. Midwest Symp. on Circuits and Systems (Ames, Iowa, 1996).

12. J. A. Starzyk and D. Nelson, "Independent Classifiers in Ontogenic Neural Networks for ATR", Adaptive Distributed Parallel Computing Symposium (Fairborn, OH, 1996).

13. J. A. Starzyk and S. Chai, "Object representation using Fourier descriptors in pattern classification", Proc. Artificial Neural Networks in Engineering Conf. (St. Louis, MO, 1995).

14. J. A. Starzyk and Ying-Wei Jan, "Low Power Voltage Based Winner Takes All Circuit for Analog Neural Networks", OAI Neural Network Symposium, (Athens, OH, 1995).

15. J. A. Starzyk and Xingyuan Lee, "Rapid Object Identification Based on Fourier Descriptors", OAI Neural Network Symposium, (Athens, OH, 1995).

16. X. Fang and J. A. Starzyk, "VLSI design of neural network based image processor", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

17. J. A. Starzyk and Y-W. Jan, "Algorithm and architecture for feature extraction in image processong", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

18. J. A. Starzyk and S. Chai, "Supervised learning with potentials for neural network- based object recognition", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

19. J. A. Starzyk and C-H. Chen, "A VLSI inner-product processor for real-time DSP applications", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

20. J. A. Starzyk and M. SenthilKumar, "Partial arithmetic - algorithms and architecture", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994).

21. J. A. Starzyk, Z. H. Liu, and J. Zou, "An organization of the test bus for analog and mixed-signal systems", Proc. of IEEE VLSI Test Symposium, (Cherry Hill, N.J. 1994).

22. X. Fang and J. Starzyk, "A novel winner-take-all circuit", the World Conf. on Neural Networks, (Portland, OR, 1993).

23. J. A. Starzyk and J. Zou, "On-line error detection in analog and mixed-signal systems", IEEE Int. Test Conference, (Baltimore, MD, 1993).

24. J. A. Starzyk and X. Fang, "System level design of a complex neural network for target recognition", IEEE Int. Conf. on Neural Network Applications to Signal Processing, (Singapore, 1993).

25. J. A. Starzyk and C.-H. Chen, "A VLSI Inner Product Processor with Built-in Self Test for Real Time DSP Applications", Int. Conf. on Signal Proc. Applications and Technology, (Santa Clara, CA, 1993).

26. J. A. Starzyk and C. H. Chen, "A One Dimensional Processor Array for LU Decomposition", Proc. IEEE Int. Workshop on Intelligent Signal Processing and Communication Syst. (Taipei, Taiwan, ROC, 1992).

27. J. A. Starzyk and N. Ansari, "Feedforward Neural Network for Handwritten Character Recognition", Proc. IEEE Int. Symp. Circuits and Systems (San Diego, CA, 1992).

28. J. A. Starzyk and H. Dai, "Noninvasive Voltage Measurement Through an On-Chip Test Structure", Proc. IEEE Int. Test Conference (Baltimore, MD, 1992).

29. J. A. Starzyk and S.K. Chai, "Vector Contour Representation for Object Recognition in Neural Networks", IEEE Int. Conf. Systems, Man, and Cybernetics, (Chicago, IL, 1992).

30. J. A. Starzyk and N. Ansari, "Distance Field Approach to Handwritten Character Recognition", Proc. Fifth Conf. on Neural Networks and Parallel Distributed Processing, (Fort Wayne, IN, 1992).

31. J. A. Starzyk and H. Dai, "Automated Testing Using Circuit Decomposition", Proc. IEEE Instr. Measurement Technology Conf. (Atlanta, GA, 1991).

32. J. A. Starzyk and X. Wu, "Approximation Using Linear Fitting Neural Network", Proc. Artificial Neural Networks in Engineering Conf. (St. Louis, MO, 1991).

33. J. A. Starzyk, "Neural Networks in Analog Fault Diagnosis", VII Riunione Annuale Dei Ricercatori, (Trani, Italy, 1991).

34. J. A. Starzyk and H. Dai, "A Decomposition Approach for Parameter Identification in Large Scale Networks," Proc. IEEE Int. Symp. Circuits and Systems (New Orleans, LA, 1990).

35. J. A. Starzyk and M. El-Gamal, "Artificial Neural Network for Testing Analog Circuits", Proc. IEEE Int. Symp. Circuits and Systems (New Orleans, LA, 1990).

36. J. A. Starzyk and M. Eshghi, "Highly Parallel Adaptive Filter," Proc. IEEE Int. Symp. Circuits and Systems (Portland, OR, 1989).

37. J. A. Starzyk and E. Sliwa, "Tolerances in Symbolic Network Analysis," Proc. IEEE Int. Symp. Circuits and Systems (Portland, OR, 1989) - invited paper.

38. J. A. Starzyk and H. Dai, "Time Domain Testing of Large Nonlinear Circuits," Proc. European Conf. Circuit Theory and Design, (Brighton, United Kingdom, 1989).

39. J. A. Starzyk and H. Dai, "Sensitivity Based Testing of Nonlinear Dynamic Circuits", Proc. IEEE Int. Symp. Circuits and Systems (Espoo, Finland, 1988).

40. J. A. Starzyk and M. A. El-Gamal, "Diagnosability of Analog Circuits a Graph Theoretical Approach", Proc. IEEE Int. Symp. Circuits and Systems (Espoo, Finland, 1988).

41. J. A. Starzyk and H. Dai, "Fault Diagnosis and Calibration of Large Analog Circuits", Proc. IEEE Int. Symp. Circuits and Systems (Espoo, Finland, 1988).

42. J. A. Starzyk and M. El-Gamal, "Fault Diagnosis of Nonlinear Resistive Circuits", Proc. 31st Midwest Symp. on Circuits and Systems (St. Louis, MO, 1988).

43. J. A. Starzyk and H. Dai, "Multifrequency Measurement of Testability in Analog Circuits", Proc. IEEE Int. Symp. Circuits and Systems (Philadelphia, PA, 1987).

44. J. A. Starzyk and M. A. El-Gamal, "An Optimization Approach to Fault Location in Analog Circuits", Proc. European Conf. Circuit Theory and Design (Prague, 1985).

45. J. A. Starzyk and V.S.R. Dandu, "Overlapped Multi-Bit Scanning Multiplier", Proc. IE: VLSI in Computers (Port Chester, NY, 1985).

46. J. A. Starzyk and H. Dai, "Element Evaluation in the Resistive Networks", Proc. 28th Midwest Symp. on Circuits and Systems (Louisville, Kentucky, 1985).

47. J. A. Starzyk and S. C. Rastogi, "Hierarchical Decomposition Approach to D.C. Power Flow Solution", Proc. 28th Midwest Symp. on Circuits and Systems (Louisville, Kentucky, 1985).

48. J. A. Starzyk and M. A. El-Gamal, "Topological Conditions for Element Evaluation", Proc. 28th Midwest Symp. on Circuits and Systems (Louisville, Kentucky, 1985).

49. J. A. Starzyk, "Decomposition Approach to a VLSI Symbolic Layout with Mixed Constraints", Proc. IEEE Int. Symp. Circuits and Systems (Montreal, 1984). pp. 457-460.

50. J. A. Starzyk and J. W. Bandler, "Design of Tests for Parameter Evaluation within Remote Inaccessible Faulty Subnetworks", Proc. IEEE Int. Symp. Circuits and Systems (Newport Beach, CA, 1983), pp. 1106-1109.

51. A. E. Salama, J. A. Starzyk and J. W. Bandler, "A Unified Decomposition Approach for Fault Location in Large Analog Circuits", Proc. European Conf. Circuit Theory and Design (Stuttgart, 1983).

52. J. A. Starzyk and J. W. Bandler, "Nodal Approach to Multiple-Fault Location in Analog Circuits", Proc. IEEE Int. Symp. Circuits and Systems (Rome, 1982), pp. 1136-1139.

53. J. W. Bandler, R. M. Biernacki, A. E. Salama and J. A. Starzyk, "Fault Isolation in Linear Analog Circuits Using the Ll Norm", Proc. IEEE Int. Symp. Circuits and Systems (Rome, 1982), pp. 1140-1143.

54. H. Gupta, J. W. Bandler, J. A. Starzyk and J. Sharma, "A Hierarchical Decomposition Approach for Network Analysis", Proc. IEEE Int. Symp. Circuits and Systems (Rome, 1982), pp. 643-646.

55. R. M. Biernacki and J. A. Starzyk, "A Test Generation Algorithm for Parameter Identification of Analog Circuits", Proc. European Conf. Circuit Theory and Design, (The Hague, 1981), pp. 993-997.

56. G. Centkowski, J. A. Starzyk and E. Sliwa, "Symbolic Analysis of Large LLS Networks by Means of Upward Hierarchical Analysis", Proc. European Conf. Circuit Theory and Design (The Hague, 1981), pp. 358-361.

57. A. Konczykowska and J. A. Starzyk, "Computer Justification of Upward Topological Analysis of Signal-Flow Graphs", Proc. European Conf. Circuit Theory and Design, (The Hague, 1981), pp. 464-467.

58. G. Centkowski, J. A. Starzyk and E. Sliwa, "Computer Implementation of Topological Methods in the Analysis of Large Networks", Proc. European Conf. Circuit Theory and Design (Warsaw, 1980), pp. 69-74.

59. A. Konczykowska and J. A. Starzyk, "Computer Analysis of Large Signal Flowgraphs by Hierarchical Decomposition Method", Proc. European Conf. Circuit Theory and Design (Warsaw, 1980), pp. 408-413.

60. R. M. Biernacki and J. A. Starzyk, "Sufficient Test Conditions for Parameter Identification of Analog Circuits Based on Voltage Measurements", Proc. European Conf. Circuit Theory and Design (Warsaw, 1980), pp. 233-241.

61. J. A. Starzyk, "An Efficient Cluster Algorithm", Proc. of 5th Czech-Polish Workshop on Circuit Theory (Podbierady, 1980).

62. J. A. Starzyk and E. Sliwa, "Topological Analysis by Hierarchic Decomposition Method", Fourth Int. Symp. on Network Theory (Ljubljana, 1979), pp. 155-160.

63. J. A. Starzyk and A. Konczykowska, "Hierarchical Decomposition of Signal-Flow Graphs", Third Int. Conf. Electronic Circuits (Prague, 1979), pp. 248-251.

64. J. A. Starzyk, "Advanced Topological Analysis", Proc. of 4th Polish-Czech Workshop on Circuit Theory (Bocheniec, 1979), pp. 90-94.

65. J. A. Starzyk, "The Distor Graphs", Proc. of 3rd Czech-Polish Workshop on Circuit Theory (Prenet, 1978).

66. J. A. Starzyk, "Topological Synthesis of Linear Network with Grounded Operational Amplifiers", Proc. of 2nd Polish-Czech Workshop on Circuit Theory (Czarlino, 1977), pp. 201-206.

67. J. A. Starzyk, "Edge Orientation in Topological Synthesis of Linear Networks", Fifth Symp. Mathematical Methods in Electrical Engineering, (Podlesice, 1976), (in Polish), pp. 169-179.

68. J. A. Starzyk, "Selected Topics in Topological Synthesis of Networks by the Method of Structural Numbers", Symp. for XXV Anniversary of Electrical Engineering Dept. (Warsaw, 1976), (in Polish), pp. 116-117.

69. J. A. Starzyk, "Topological Synthesis of Linear Active Networks with the Method of Structural Numbers", Proc. European Conf. Circuit Theory and Design (Genova, 1976), pp. 340-348.

70. J. A. Starzyk, "Problems in Topological Analysis", First National Conf. URSI (Warsaw, 1975), (in Polish), pp. 250-252.

71. J. A. Starzyk, "Topological Synthesis of Multivariable Network Functions", Third Int. Symp. on Network Theory (Split, 1975), pp. 555-564.

72. J. A. Starzyk, "Complement of Set of Trees", Eight Asilomar Conf. Circuits, Systems and Computers, (Pacific Grove), 1974, pp. 227-230.