617 Fault Testable Design
Course Description
This course aims to convey a knowledge of basic concepts of reliability,
functional modeling, logic simulation, fault modeling, fault simulation,
test generation for combinational logic circuits, detection of multiple
faults in digital circuits, test generation for sequential logic circuits,
random testing and signature analysis, design for testability, concepts
of fault tolerance and circuit redundancy, built-in test, boundary scan
standards, compression techniques, and self testing. Students will implement
learned design for testability techniques in their own designs, using Mentor
Graphics testing tools and circuit simulation packages installed on Sun
workstations. Special attention will devoted to the most important challenges
facing digital circuit designers today and in the coming decade, being
the impact of CAD tools in design and testing of integrated circuits, integration
of logic and test circuitry, and modern testing techniques. This will reflected
in both the lectures and the preferred projects.
Syllabus
Schedule
Reference Books
VLSI Design
Laboratory
Using VHDL
in Testing
VLSI design and CAD sites
Computer Society
Design and Test
MIT's Semiconductor Subway
Links
MOSIS VLSI Fabrication
CAD Research
Labs
Career Mosaic