My research interests include Network-on-Chips (NoCs), emerging technologies (nanophotonics, wireless, 3D), 
hardware security, IoT, computer architecture, and exascale networks. Below, I elaborate on some of my current
research projects.
 Current Research

IntelliNoC: Intelligent NoC with Machine Learning
A key challenge in addressing optimized NoC architecture design today is the plethora of performance enhancing,
energy-efficient and fault tolerant techniques available to NoC designers and the large design space that must be
navigated to simultaneously reduce power, improve reliability, increase performance and maintain QoS. Manually
designing rules for optimizing such competing trade-offs is likely to require a substantial engineering effort, which,
in turn, is bound to result in suboptimal solutions, given the combinatorial size of the decision space and the
complexity of the interactions between decisions made for various NoC components. Machine Learning (ML)
techniques can work with high dimensional inputs and can be used to automatically infer complex decisions in
order to optimize designs. This research proposes a new cross-layer, cross-cutting methodology spanning
circuits, architectures, machine learning algorithms, and applications, aimed at designing energy-efficient,
reliable and scalable NoCs.
Selected Papers:
Hardware Security
With each technology generation, security concerns for integrated circuits (IC) will continue to grow as malicious 
attackers find new ways to compromise critical computing systems. As aggressive transistor scaling continues
according to Moore's law, the ability to detect any malicious alterations which is achieved by additional transistors/circuits
will become more difficult with each technology generation. As multicores require NoC architectures to meet communication
requirements, NoCs should provide security measures to protect sensitive data from fault injection attacks between IP cores
while ensuring functional correctness to prevent systems from failing.
Selected Papers:
Improving Reliability of NoCs
While multicores are facilitating an enormous integration capacity, aggressive transistor scaling has led to steady 
degradation of device and circuit reliability. This research proposes to develop a holistic design methodology that
addresses the reliability of the entire NoC communication infrastructure while minimizing energy footprint, reducing
area overhead and marginally impacting performance.

Selected Papers:
Silicon Photonic Based Network-on-Chip Architectures

As on-chip power consumption becomes the most critical barrier, we need disruptive technology solution such as
silicon photonics that can scale in capacity and reduce power footprint while delivering scalable bandwidth. Photonic
interconnects can provide high interconnect bandwidth by combining multiple wavelengths, provide minimal access
latencies, and high power-efficiency that remains independent of capacity and distance for on-chip communications.
In this research, we explore several aspects of utilizing photonics for NoCs such as
power-efficiency, programmability,
cache coherence, reliability, bandwidth reconfiguration, technology exploration and heterogeneity.

Selected Papers:

Wireless Optical Network-on-Chips (WiNoC)

As wireless technology offers several advantages such as one-hop unicast, multicast and broadcast communication,
multiple degrees of freedom (spatial, temporal and frequency domains), and mature technology, we propose to combine
both optics and wireless to scale NoCs to kilo-core and beyond topologies. In this research, we will evaluate the design
trade-offs in integrating multiple technologies and analyze poiwer and performance for diverse scientific applications.

Selected Papers:
Exascale and Datacenter Photonic Networks for HPC
At the off-chip level, we used optical interconnects to scale network topologies by providing sufficient inter-core 
and inter-node bandwidth. We developed a design methodology for exascale and datacenter architectures using
photonic interconnects by building local and global networks using scalable topologies such as Dragonfly, Butterfly
and k-ary n-cube networks with the goals of reducing radix, diameter and hop counts.
Selected Papers: