My research interests include Network-on-Chips (NoCs), emerging technologies (nanophotonics, wireless, 3D), 
hardware security, IoT, computer architecture, and exascale networks. Below, I elaborate on some of my current 
research projects.

A key challenge in addressing optimized NoC architecture design today is the plethora of performance enhancing,
energy-efficient and fault tolerant techniques available to NoC designers and the large design space that must be
navigated to simultaneously reduce power, improve reliability, increase performance and maintain QoS. Manually
designing rules for optimizing such competing trade-offs is likely to require a substantial engineering effort, which,
in turn, is bound to result in suboptimal solutions, given the combinatorial size of the decision space and the
complexity of the interactions between decisions made for various NoC components. Machine Learning (ML)
techniques can work with high dimensional inputs and can be used to automatically infer complex decisions in
order to optimize designs. This research proposes a new cross-layer, cross-cutting methodology spanning
circuits, architectures, machine learning algorithms, and applications, aimed at designing energy-efficient, 
reliable and scalable NoCs.

• Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques [TC-2018]
  
• LEAD: Learning-enabled Energy-Aware Dynamic Voltage/Frequency Scaling in NoCs [DAC-2018]
• Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning [HPCA-2018]
• Machine Learning Enabled Power-Aware Network-on-Chip Design [DATE-2017]
• Dynamic Error Mitigation in NoCs using Intelligent Prediction Techniques [MICRO-2016]
• Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures [TC-2015]

With each technology generation, security concerns for integrated circuits (IC) will continue to grow as malicious 
attackers find new ways to compromise critical computing systems. As aggressive transistor scaling continues 
according to Moore's law, the ability to detect any malicious alterations which is achieved by additional transistors/circuits 
will become more difficult with each technology generation. As multicores require NoC architectures to meet communication 
requirements, NoCs should provide security measures to protect sensitive data from fault injection attacks between IP cores 
while ensuring functional correctness to prevent systems from failing.

• GARUDA: Designing Energy-Efficient Hardware Monitors from High-Level Policies for Secure Information Flow [CASES-2018]
• Securing NoCs Against Timing Attacks with Non-Interference Based Adaptive Routing [NoCs-2018]
• Mitigation of Hardware Trojan based Denial-of-Service Attack for Secure NoCs [JPDC-2018]
• Secure Model Checkers for Network-on-Chip (NoC) Architecture [GLSVLSI-2016]
• Mitigation of Denial-of-Service Attack with Hardware Trojans in NoC Architecture [IPDPS-2016]
• Packet Security with Path Sensitization for NoCs [DATE-2016]

While multicores are facilitating an enormous integration capacity, aggressive transistor scaling has led to steady 
degradation of device and circuit reliability. This research proposes to develop a holistic design methodology that 
addresses the reliability of the entire NoC communication infrastructure while minimizing energy footprint, reducing 
area overhead and marginally impacting performance. 

Selected Papers: 

• Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs [JETC-2018]
• RETUNES: Reliable and Energy-Efficient Network-on-Chip Architecture [ICCD-2018]
• Runtime Fault Tolerant Techniques to Migitate Soft Errors in Network-on-Chips (NoCs) Architecture [TCAD-2018]
• Dynamic Error Mitigation in NoCs using Intelligent Prediction Techniques [MICRO-2016]
• An Adaptive Algorithm to Improve Lifetime Reliability in NoCs Architecture [DFT-2016]
• Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures [TC-2015]

As on-chip power consumption becomes the most critical barrier, we need disruptive technology solution such as
silicon photonics that can scale in capacity and reduce power footprint while delivering scalable bandwidth. Photonic
interconnects can provide high interconnect bandwidth by combining multiple wavelengths, provide minimal access
latencies, and high power-efficiency that remains independent of capacity and distance for on-chip communications.
In this research, we explore several aspects of utilizing photonics for NoCs such as power-efficiency, programmability,
cache coherence, reliability, bandwidth reconfiguration, technology exploration and heterogeneity.

• SHARP: Shared Heterogeneous Architecture with Reconfigurable Photonic Network-on-Chip [JETC-2018]
• Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning [HPCA-2018]
• Laser Pooling: Static and Dynamic Laser Power Allocation for On-Chip Optical Interconnects [JLT-2017]
• CLAP-NET: Bandwidth Adaptive and Power Regulated Optical Crossbar Architecture [JPDC-2017]
• Cross-Chip: Low Power Processor-to-Memory Nanophotonic Interconnect Architecture [IGSC-2015]
• Runtime Power Reduction Techniques in On-Chip Photonic Interconnect [GLSVLSI-2015]

As wireless technology offers several advantages such as one-hop unicast, multicast and broadcast communication,
multiple degrees of freedom (spatial, temporal and frequency domains), and mature technology, we propose to combine
both optics and wireless to scale NoCs to kilo-core and beyond topologies. In this research, we will evaluate the design
trade-offs in integrating multiple technologies and analyze poiwer and performance for diverse scientific applications.

• Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies [TSUC-2018]
• Sub-THz Tunable Push-Push Oscillators with FinFETs for Wireless NoCs [MWSCAS-2018]
• Scalable Power-Efficient Kilo-Core Photonic-Wireless NoC Architecture [IPDPS-2018]
• Monopoles Loaded with 3D-Printed Dielectrics for Future Wireless Intra-Chip Communications [TAP-2017]
• Antennas and Channel Characteristics for Wireless Network-on-Chips [WPC-2017]
• Reconfigurable Optical and Wireless (R-OWN) Network-on-Chip for High Performance Computing [NANOCOM-2016]
• Exploring Wireless Technology for Off-Chip Memory Access [HotI-2016]

At the off-chip level, we used optical interconnects to scale network topologies by providing sufficient inter-core 
and inter-node bandwidth. We developed a design methodology for exascale and datacenter architectures using 
photonic interconnects by building local and global networks using scalable topologies such as Dragonfly, Butterfly 
and k-ary n-cube networks with the goals of reducing radix, diameter and hop counts.

• Scalable 3D Optical Interconnects for Datacenters [Elsevier-2016]
• Power and Performance Analysis of Scalable Photonic Networks for Exascale Architecture [IGSC-2015]
• Photonic Interconnects for Exascale and Datacenter Architecture [MICROMag-2014]
  
• SPRINT: Scalable Photonic Switching Fabric for High-Performance Computing [JOCN-2012]
• Energy-Efficient and Bandwidth Reconfigurable Photonic Networks for HPC Systems [JSTQE-2011]