I received my PhD and MS from Electrical and Computer Engineering Department from The University of Arizona
in August 2006 and May 2003 respectively. I completed my BE in Electronics and Communications in February 2000
from Manipal Institute of Technology, Mangalore University. I was a post-doctoral scholar at the High-Performance
Computing Architectures and Technologies (HPCAT) Laboratory at The University of Arizona from 2006 to 2007.
I was a consultant to Advanced Micro Devices (AMD) on Exascale and FastForward initiatives sponsored by
Department of Energy from 2013-2017.
Presently, I am the Director & Chair of the School of Electrical Engineering and Computer Science as well as Joseph K.
Jachinowski Professor in the School of Electrical Engineering and Computer Science at Ohio University. I lead the
Technologies for Emerging Computer Architecture Laboratory (TEAL) at Ohio University.
My research interests include computer architecture, optical interconnects, Network-on-Chips (NoCs) and emerging
technologies such as nanophotonics, 3D and wireless interconnects. I am the recipient of the NSF CAREER Award
(2011), Presidential Research Scholar Award (2017), Best Paper Award at the ICCD (2013) conference and my
papers have been nominated for Best Paper at IEEE High-Performance Computing, Data & Analytics (HiPC) in Dec 2021,
IEEE Design and Test in Europe (DATE) in March 2019, IEEE Symposium on Network-on-Chips (NoCs) in May 2010 and
IEEE Asia & South Pacific Design Automation Conference (ASP-DAC) in January 2009. My 2004 Hot Interconnects paper
was selected as one of the Top Picks for IEEE MICRO magazine in 2005.
I have served as an Associate Editor for IEEE Transactions on Computers (2019-2023), IEEE Transactions on Cloud
Computing (2021-) and I have been a co-Guest Editor for IEEE Transactions on Emerging Topics for Computing ('15-'16) and
Journal of Parallel and Distributed (JPDC) ('10-'11). I am the Vice-Chair for Architecture area for IPDPS-2020 and I have been
on the Program Committee of ISCA'24, HPCA'19, DAC ('18,'19,'20, '21, '22), NAS'17, NoCs ('16, '17, '18, '19, '20, '21),
MPSoCs ('14, '15, '16, '17, '18, '19), HiPC ('21,'22) ACM Nanocom '16, Hot Interconnects ('10,'15,'16,'17),
external Program Committee for MICRO'12 and HPCA'17.
- Best Paper Candidate - IEEE
High-Performance Computing, Data & Analytics (HiPC), Dec
2021
- IEEE Transactions on Computing
Award for Editorial Service and Excellence - 2020, 2021
- Marvin E. and Ann D. White
Research Award - Russ College of Engineering and Technology -
2020, 2014, 2012
- Best Paper Candidate - IEEE
Design and Test in Europe (DATE), March 2019
- Presidential Research Scholar
Award - October 2017
- Best Paper - IEEE Conference on
Computer Design (ICCD) - October 2013
- NSF CAREER Award - 2011
- Outstanding Research Paper Award
- Russ College of
Engineering and Technology - May 2011
- Best Paper Candidate - IEEE
Symposium on Network-on-Chips (NoCs), May 2010
- Best Paper Candidate - IEEE Asia
& South Pacific Design Automation Conference (ASP-DAC),
January 2009
- IEEE MICRO Top Picks from IEEE
Hot Interconnects'04, August 2004
- First Class with Distinction -
Bachelors of Engineering, February 2000
- Computer Architecture
- Network-on-Chips (NoCs)
- Hardware Security
- Emerging Technologies for NoCs (Nanophotonics,
Wireless, 3D Integration)
- Machine Learning for Computing Systems
A Silicon
Photonic Multi-DNN Accelerator [PACT'23]
Flumen: Dynamic Procesing in the Photonic Interconnect
[ISCA'23]
SPACX: Silicon Photonics-based Scalable
Chiplet Accelerator for DNN Inference [HPCA'22]
Albiero: Energy-Efficient Acceleration of
Convolutional Neural Networks via Silicon Photonics [ISCA'21]
Scaling Deep Learning Inference
with Chiplet-based Architecture and Photonic Interconnects [DAC'21]
CSCNN: Algorithm-Hardware Co-Design for CNN Accelerators using
Centrosymmetric Filters [HPCA'21]
GCNAX: A Flexible Dataflow
Accelerator for Graph Convolution Neural Network [HPCA'21]
Last Updated
January 2, 2024
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