Note: Screencasts are available via on blackboard https://blackboard.ohio.edu/

Module 7: On-Chip Networks

4/24: L08 - On-Chip Networks

Screencasts -L08-1,2,3,4

Reading Assignment –

• Natalie Enright Jerger and Li-Shuian Peh, "On-Chip Networks," Synthesis Lectures in Computer Architecture
  
• Daniel Sorin, Mark D. Hill and David A. Wood, "A Primer on Memory Consistency and Cache Coherence".
  

Module 6: Multiprocessors

4/1: L07 - Multiprocessors

Screencasts -L07-1,2,3,4,5,6,7,8,9,10

Reading Assignment –

• Chapter 5
• Daniel Sorin, Mark D. Hill and David A. Wood, "A Primer on Memory Consistency and Cache Coherence".
  

Module 5: Cache and Memory

3/6: L06A - Cache

3/20: L06B - Memory

Screencasts -L06A-1,2,3,4,5,6,7,8; L06B-1,2,3,4,5,6,7,8,9;

Reading Assignment –

• Appendix B - Review of Memory Hierarchy
  
• Chapter 2
• Non-Volatile Memory: Emerging Technologies and Their Impact on Memory Systems

Module 4: Multithreading

2/19: L05A - Thread Level Parallelism

2/23: L05B - Data Level Parallelism

Screencasts -L05A-1,2,3,4,5,6; L05B-1,2,3,4,5,6,7,8;

Reading Assignment –

• Textbook 3.12, 4.1-4.4
• (optional) Susan Eggers, et.al. "Simultaneous Multithreading: A Platform for Next Generation Processors," IEEE Micro, pp. 12-19, September/October 1997.
• (optional) Poonacha Kongetira, et. al, "Niagara: A 32-way Multithreading Sparc Processor," IEEE Micro, pp. 21-29, March/April 2005.
• (optional) NVIDIA's Next Generation CUDA Compute Architecture
  

Module 3: Instruction Level Parallelism

2/2: L04A - Instruction Level Parallelism

2/5: L04B - Dynamic Scheduling

2/7: L04C - Speculation

Screencasts -L04A-1,2,3,4,5,6; L04B-1,2,3,4,5,6,7; L0C-1,2,3,4,5,6,7,8,9,10,11,12,13

Reading Assignment –

• Textbook 3.1-3.11
• (Optional)  S. Farling, "Combining Branch Predictors" Tech. Report TN-36, Western Research Lab, DEC, Palo Alto, June 1993.
  

Module 2: Instruction Set Architecture (ISA) Review

1/24: Review- ISA

Screencasts - ISA-1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16

Reading Assignment –

• Textbook Appendix A and C

Module 1: Introduction to Computer Architecture and Performance Metrics

1/19: Metrics

1/17: Introduction to Computer Architecture

Screencasts - Intro-1, 2, 3, 4, 5 and Metrics-1, 2, 3, 4, 5, 6, 7, 8, 9

Reading Assignment –

• Textbook Chapter 1

• (Optional) “The Landscape of Parallel Computing Research: A View from Berkeley” by Krste Asanovic, et. al. http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-183.html

• (Optional) Kalray Manycore Architecture: http://www.kalray.eu/IMG/pdf/FLYER_MPPA_MANYCORE.pdf

• (Optional) Per Hammarland “4^th Generation Intel Core Processor, codenamed Haswell” http://www.hotchips.org/wp-content/uploads/hc_archives/hc25/HC25.80-Processors2-epub/HC25.27.820-Haswell-Hammarlund-Intel.pdf

• (Optional) Mark Hill and Micheal Marty, “Amdahl’s Law in the Multicore Era,” IEEE Computer, pp, 23-38, July 2008; http://research.cs.wisc.edu/multifacet/papers/ieeecomputer08_amdahl_multicore.pdf

• (Optional) Daniel Sorin, “Fault Tolerant Computer Architecture,” Synthesis Lectures on Computer Architecture: http://www.morganclaypool.com/doi/abs/10.2200/S00192ED1V01Y200904CAC005